参数资料
型号: MAX6960AMH+D
厂商: Maxim Integrated
文件页数: 18/34页
文件大小: 0K
描述: IC DRVR LED 8X8 44-MQFP
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 96
显示器类型: LED
配置: 8 x 8(矩阵)
接口: 4 线串行
数字或字符: 任何数字类型
电流 - 电源: 7.5mA
电源电压: 2.7 V ~ 3.6 V
工作温度: -40°C ~ 125°C
安装类型: 表面贴装
封装/外壳: 44-QFP
供应商设备封装: 44-MQFP(10x10)
包装: 管件
MAX6960–MAX6963
4-Wire Serially Interfaced
8 x 8 Matrix Graphic LED Drivers
Table 15. Global Panel Configuration Register Format
REGISTER
ADDRESS
CODE (HEX)
D7
D6
D5
REGISTER DATA
D4 D3
D2
D1
D0
Global panel configuration
0x0D
PI
C
F
R
DP1
DP0
IP
S
Table 16. Global Panel Configuration—Shutdown Control (S Data Bit D0) Format
REGISTER
ADDRESS
CODE (HEX)
D7
D6
D5
REGISTER DATA
D4 D3
D2
D1
D0
Shutdown
Normal operation
0x0D
0x0D
PI
PI
C
C
F
F
R
R
DP1
DP1
DP0
DP0
IP
IP
0
1
Table 17. Global Panel Configuration—Invert Pixels (IP Data Bit D1) Format
REGISTER
ADDRESS
CODE (HEX)
D7
D6
D5
REGISTER DATA
D4 D3
D2
D1
D0
Logic 1 in display memory lights the appropriate
LED (normal logic)
Logic 0 in display memory lights the appropriate
LED (invert logic)
0x0D
0x0D
PI
PI
C
C
F
F
R
R
DP1
DP1
DP0
DP0
0
1
S
S
Table 18. Global Panel Configuration—Current Plane (DP0, DP1 Data Bit D2, D3) Format
REGISTER
ADDRESS
CODE (HEX)
D7
D6
D5
REGISTER DATA
D4 D3
D2
D1
D0
Current display plane is P0
Current display plane is P1
Current display plane is P2
Current display plane is P0
Current display plane is P3
Current display plane is P1
0x0D
0x0D
0x0D
0x0D
0x0D
0x0D
PI
PI
0
1
0
1
C
C
C
C
C
C
F
F
F
F
F
F
R
R
R
R
R
R
0
0
1
1
1
1
0
1
0
0
1
1
IP
IP
IP
IP
IP
IP
S
S
S
S
S
S
Initial Power-Up
The power-up sequence consists of an internal power-on
reset (POR), assertion of the external reset input RST ,
and auto-address configuration (see the Local 3-Wire
Interface section). The internal POR resets all control
registers to the default values shown in Table 12.
After RST goes high an internal timer delays execution of
the auto-address configuration for 2 21 (2,097,152) OSC
cycles (nominally 250ms at OSC = 4.194MHz) (see the
3-Wire Interface Clock (ADDCLK ) section). During this
delay time, the global driver devices register (0x0E),
global driver rows register (0x0F), and global panel con-
figuration register (0x0D) should be written as these
18
values are used in the auto-address configuration
sequence (see the Device Configuration section). After
the internal delay time, the auto-addressing configuration
commences and takes a fixed interval of 256 ADDCLK
cycles to complete where the ADDCLK frequency is
OSC/4 (see the 3-Wire Interface Clock (ADDCLK) sec-
tion). After completing the auto-self-addressing of all
possible 256 interconnected devices, all of the
MAX6960s enter shutdown mode.
All registers are capable of write device register opera-
tions during the internal delay interval using the 4-wire
serial interface. Read device register operations are not
allowed during auto-address configuration.
Maxim Integrated
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MAX6960ATH+T 功能描述:LED显示驱动器 8x8 Matrix Graphic LED Driver RoHS:否 制造商:Micrel 数位数量:5 片段数量: 安装风格:SMD/SMT 封装 / 箱体:PLCC-44 工作电源电压:4.75 V to 11 V 最大电源电流:10 mA 最大工作温度:+ 85 C 最小工作温度:- 40 C 封装:Tube
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