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参数资料
| 型号： | MAX6965AEE+T |
| 厂商： | Maxim Integrated |
| 文件页数： | 3/22页 |
| 文件大小： | 0K |
| 描述： | IC LED DRIVER LINEAR 16-QSOP |
| 产品培训模块： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 标准包装： | 2,500 |
| 拓扑： | 开路漏极，PWM |
| 输出数： | 9 |
| 内部驱动器： | 是 |
| 类型 - 主要： | 背光，LED 闪烁器 |
| 类型 - 次要： | RGB，白色 LED |
| 频率： | 400kHz |
| 电源电压： | 2 V ~ 3.6 V |
| 输出电压： | 7V |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 16-SSOP（0.154"，3.90mm 宽） |
| 供应商设备封装： | 16-QSOP |
| 包装： | 带卷 (TR) |
| 工作温度： | -40°C ~ 125°C |
9-Output LED Driver with Intensity Control
and Hot-Insertion Protection
ELECTRICAL CHARACTERISTICS (continued)
(Typical Operating Circuit, V+ = 2V to 3.6V, T A = T MIN to T MAX , unless otherwise noted. Typical values are at V+ = 3.3V, T A = + 25°C.)
(Note 1)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
T A = +25°C
0.15
0.25
V+ = 2V, I SINK = 20mA
T A = -40°C to +85°C
T A = T MIN to T MAX
0.29
0.31
Output Low Voltage
O0–O8
V OL
V+ = 2.5V, I SINK = 20mA
T A = +25°C
T A = -40°C to +85°C
0.13
0.22
0.25
V
T A = T MIN to T MAX
0.27
T A = +25°C
0.12
0.22
V+ = 3.3V, I SINK = 20mA
T A = -40°C to +85°C
T A = T MIN to T MAX
0.23
0.25
Output Low-Voltage SDA
PWM Clock Frequency
V OLSDA
f PWM
I SINK = 6mA
32
0.4
V
kHz
TIMING CHARACTERISTICS
(Typical Operating Circuit, V+ = 2V to 3.6V, T A = T MIN to T MAX , unless otherwise noted. Typical values are at V+ = 3.3V, T A = +25°C.)
(Note 1)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Serial Clock Frequency
Bus Free Time Between a STOP and a START
Condition
Hold Time, Repeated START Condition
Repeated START Condition Setup Time
STOP Condition Setup Time
f SCL
t BUF
t HD, STA
t SU, STA
t SU, STO
1.3
0.6
0.6
0.6
400
kHz
μs
μs
μs
μs
Data Hold Time
Data Setup Time
SCL Clock Low Period
SCL Clock High Period
t HD, DAT
t SU, DAT
t LOW
t HIGH
(Note 2)
180
1.3
0.7
0.9
μs
ns
μs
μs
Rise Time of Both SDA and SCL Signals, Receiving
Fall Time of Both SDA and SCL Signals, Receiving
Fall Time of SDA Transmitting
t R
t F
t F.TX
(Notes 3, 4)
(Notes 3, 4)
(Notes 3, 5)
20 +
0.1C b
20 +
0.1C b
20 +
0.1C b
300
300
250
ns
ns
ns
Pulse Width of Spike Suppressed
Capacitive Load for Each Bus Line
t SP
C b
(Note 6)
(Note 3)
50
400
ns
pF
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