参数资料
型号: MAX6975ATL+T
厂商: Maxim Integrated
文件页数: 17/23页
文件大小: 0K
描述: IC LED DRIVER LINEAR 40-TQFN
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 2,500
拓扑: PWM
输出数: 24
内部驱动器:
类型 - 主要: 通用
类型 - 次要: RGB
频率: 33MHz
电源电压: 3 V ~ 3.6 V
输出电压: 7V
安装类型: 表面贴装
封装/外壳: 40-WFQFN 裸露焊盘
供应商设备封装: 40-TQFN-EP(6x6)
包装: 带卷 (TR)
工作温度: -40°C ~ 125°C
24-Output PWM LED Drivers
for Message Boards
segments transfer to all cascaded devices, while the
data section reduces in bit length as data transfers
through the cascaded devices. When LOADI is low, the
MAX6974/MAX6975 continuously monitor DIN for
reception of the SYNC pattern (see the Header
Segment section).
Header Segment
The 24-bit header segment consists of an 8-bit fixed
synchronization pattern (SYNC), a 6-bit command pat-
LOADI, internally synchronizes the timing relationship
between CLKI and DIN with the LOADI signal. The
synchronization pattern must be 0xE8.
CMD[5:0]
Send command bits C1 and C0 three times in succes-
sion. The command bits define how many data bits are
received and where the data is loaded. The four com-
mands are:
tern (CMD), and a 10-bit counter (CNTR) segment (see
Table 7). LOADI must change from low to high within
plus or minus one clock cycle of the first command bit.
When the SYNC bit pattern 0xE8 is recognized, LOADI
is monitored for the rising edge, allowing the device to
internally synchronize LOADI to CLKI. The six command
C1:C0
00
01
10
11
COMMAND
Load individual PWM
Load CALDAC
Load global-intensity PDM
Load configuration
CMD[5:0]
000000
010101
101010
111111
bits, CMD[5:0], consist of bits C1 and C0 repeated
three times. The four commands used by the MAX6974/
MAX6975 are defined by the two bits, C1 and C0.
The counter segment is incremented by one for each
cascaded device with an internal fault detected. Use the
counter segment to collect fault data across the cas-
caded chain.
HDR[23:0]
Complete 24-bit header segment.
SYNC[7:0]
Synchronization bit pattern 0xE8 is recognized by the
MAX6974/MAX6975 during intervals when LOADI is low.
The SYNC bit pattern, followed by the rising edge of
Table 7. Serial-Interface Header
HDR
CNTR[9:0]
This is the counter for open LED or overtemperature fault
conditions. The host sends the header segment with the
counter value set to zero. The counter value is incre-
mented one count by each device that detects a fault
condition in the cascaded chain. The accumulated count
value returns to the host from the last device in the cas-
cade chain. The command determines which fault type
is incremented to the counter (see LED Open-Circuit and
Overtemperature Detection Counter section):
CMD[1:0] = X0 Overtemperature faults counted
CMD[1:0] = X1 Open LED faults counted
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
SYNC
CMD
CNTR
7
1
6
1
5
1
4
0
3
1
2
0
1
0
0
0
1
C1
0
C0
1
C1
0
C0
1
C1
0
C0
9
b9
8
b8
7
b7
6
b6
5
b5
4
b4
3
b3
2
b2
1
b1
0
b0
HEADER
SYNC
COMMAND
COUNTER
DATA
1
LOADI
0
DIN
1
1
1
0
1
0
0
0 C1 C0 C1 C0 C1 C0 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0
CLKI
(CONTINUOUS)
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
Figure 7. Header-Segment Timing
______________________________________________________________________________________
17
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