参数资料
型号: MAX7030LATJ+T
厂商: Maxim Integrated
文件页数: 13/20页
文件大小: 0K
描述: IC ASK TXRX 315MHZ 32-TQFN
其它有关文件: Automotive Product Guide
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 2,500
频率: 315MHz
数据传输率 - 最大: 33kbps
调制或协议: ASK,OOK
应用: 车库门开启器,遥控,双向 RKE
功率 - 输出: 10dBm
灵敏度: -114dBm
电源电压: 2.1 V ~ 3.6 V
电流 - 接收: 6.7mA
电流 - 传输: 12.5mA
数据接口: PCB,表面贴装
天线连接器: PCB,表面贴装
工作温度: -40°C ~ 125°C
封装/外壳: 32-WFQFN 裸露焊盘
包装: 带卷 (TR)
Low-Cost, 315MHz and 433.92MHz
ASK Transceiver with Fractional-N PLL
Table 1. AGC Dwell Time Settings for
MAX7030
For Manchester Code (50% duty cycle), set the dwell
time to at least twice the bit period. For nonreturn-to-
zero (NRZ) data, set the dwell to greater than the peri-
AGC2
0
0
0
0
1
1
1
1
AGC1
0
0
1
1
0
0
1
1
AGC0
0
1
0
1
0
1
0
1
DESCRIPTION
AGC disabled, high gain selected
K = 11
K = 13
K = 15
K = 17
K = 19
K = 21
K = 23
od of the longest string of zeros or ones. For example,
using Manchester Code at 315MHz (f XTAL =
12.679MHz) with a data rate of 2kbps (bit period =
250μs), the dwell time needs to be greater than 500μs:
K ≥ 3.3 x log 10 (500μs x 12.679) ≈ 12.546
Choose the AGC pin settings for K to be the next odd-
integer value higher than 12.546, which is 13. This says
that AGC1 is set high and AGC0 and AGC2 are set low.
Mixer
A unique feature of the MAX7030 is the integrated
AGC Dwell-Time Settings
The AGC dwell timer holds the AGC in low-gain state
for a set amount of time after the power level drops
below the AGC switching threshold. After that set
amount of time, if the power level is still below the AGC
threshold, the LNA goes into high-gain state. This is
important for ASK since the modulated data may have
a high level above the threshold and low level below
the threshold, which without the dwell timer would
cause the AGC to switch on every bit.
The MAX7030 uses the three AGC control pins (AGC0,
AGC1, AGC2) to set seven user-controlled, dwell-timer
settings. The AGC dwell time is dependent on the crys-
tal frequency and the bit settings of the AGC control
pins. To calculate the dwell time, use the following
equation:
image rejection of the mixer. This eliminates the need
for a costly front-end SAW filter for many applications.
The advantage of not using a SAW filter is increased
sensitivity, simplified antenna matching, less board
space, and lower cost.
The mixer cell is a pair of double-balanced mixers that
perform an IQ downconversion of the RF input to the
10.7MHz intermediate frequency (IF) with low-side
injection (i.e., f LO = f RF - f IF ). The image-rejection circuit
then combines these signals to achieve a typical 46dB
of image rejection over the full temperature range. Low-
side injection is required as high-side injection is not
possible due to the on-chip image rejection. The IF out-
put is driven by a source follower, biased to create a
driving impedance of 330 Ω to interface with an off-chip
330 Ω ceramic IF filter. The voltage-conversion gain dri-
ving a 330 Ω load is approximately 20dB. Note that the
Dwell Time =
2 K
f XTAL
MIXIN+ and MIXIN- inputs are functionally identical.
Integer-N Phase-Locked Loop (PLL)
The MAX7030 utilizes a fixed-integer-N PLL to generate
where K is an odd integer in decimal from 11 to 23, deter-
mined by the control pin settings shown in Table 1.
To calculate the value of K, use the following equation
and use the next integer higher than the calculated
result:
K ≥ 3.3 x log 10 (Dwell Time x f XTAL )
the receive LO. All PLL components, including the loop
filter, voltage-controlled oscillator, charge pump, asyn-
chronous 24x divider, and phase-frequency detector
are integrated internally. The loop bandwidth is approx-
imately 500kHz. The relationship between RF, IF, and
crystal reference frequencies is given by:
f XTAL = (f RF - f IF )/24
13
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