参数资料
型号: MAX7034AUI+T
厂商: Maxim Integrated
文件页数: 7/14页
文件大小: 0K
描述: IC RX 315MHZ/433MHZ ASK 28-TSSOP
其它有关文件: Automotive Product Guide
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 2,500
频率: 300MHz ~ 450MHz
灵敏度: -114dBm
数据传输率 - 最大: 33 kbps
调制或协议: ASK
应用: 车库门开启器,ISM,RKE,安全警报
电流 - 接收: 7.2mA
数据接口: PCB,表面贴装
天线连接器: PCB,表面贴装
电源电压: 4.5 V ~ 5.5 V
工作温度: -40°C ~ 125°C
封装/外壳: 28-TSSOP(0.173",4.40mm 宽)
供应商设备封装: 28-TSSOP
包装: 带卷 (TR)
315MHz/434MHz ASK Superheterodyne
Receiver
Pin Description (continued)
PIN
4
5, 10
6
8
9
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
NAME
LNASRC
AGND
LNAOUT
MIXIN1
MIXIN2
IRSEL
MIXOUT
DGND
DVDD
EN_REG
XTALSEL
IFIN1
IFIN2
DFO
DSN
OPP
DFFB
DSP
V DD5
DATAOUT
PDOUT
SHDN
XTAL2
FUNCTION
Low-Noise Amplifier Source for external Inductive Degeneration. Connect inductor to ground to set
LNA input impedance. See the Low-Noise Amplifier section.
Analog Ground
Low-Noise Amplifier Output. Connect to mixer input through an LC tank filter. See the Low-Noise
Amplifier section.
1st Differential Mixer Input. Connect to LC tank filter from LNAOUT through a 100pF capacitor. See
the Typical Application Circuit.
2nd Differential Mixer Input. Connect to V DD3 side of the LC tank filter through a 100pF capacitor. See
the Typical Application Circuit.
Image-Rejection Select. Set V IRSEL = 0V to center image rejection at 315MHz. Leave IRSEL
unconnected to center image rejection at 375MHz. Set V IRSEL = DVDD to center image rejection at
434MHz. See the Mixer section.
330 Ω Mixer Output. Connect to the input of the 10.7MHz bandpass filter.
Digital Ground
Positive Digital Supply Voltage. Connect to both of the AVDD pins. Bypass to DGND with a 0.01μF
capacitor as close as possible to the pin (see the Typical Application Circuit ).
Regulator Enable. Connect to V DD5 to enable internal regulator. Pull this pin low to allow device
operation between +3.0V and +3.6V. See the Voltage Regulator section.
Crystal Divider Ratio Select. Drive XTALSEL low to select f LO /f XTAL ratio of 64, or drive XTALSEL high
to select f LO /f XTAL ratio of 32.
1st Differential Intermediate-Frequency Limiter Amplifier Input. Connect to the output of a 10.7MHz
bandpass filter.
2nd Differential Intermediate-Frequency Limiter Amplifier Input. Bypass to AGND with a 1500pF
capacitor as close as possible to the pin.
Data Filter Output
Negative Data Slicer Input
Noninverting Op-Amp Input for the Sallen-Key Data Filter
Data Filter Feedback Node. Input for the feedback of the Sallen-Key data filter.
Positive Data Slicer Input
+5V Supply Voltage. Bypass to AGND with a 0.01μF capacitor as close as possible to the pin. For
+5V operation, V DD5 is the input to an on-chip voltage regulator whose +3.4V output appears at
AVDD pin 2. (see the Voltage Regulator section and the Typical Application Circuit ).
Digital Baseband Data Output
Peak-Detector Output
Power-Down Select Input. Drive high to power up the IC. Internally pulled down to AGND with a
100k Ω resistor.
Crystal Input 2. Can also be driven with an external reference oscillator. See the Crystal Oscillator section.
7
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