参数资料
型号: MAX706ASESA+T
厂商: Maxim Integrated Products
文件页数: 6/12页
文件大小: 0K
描述: IC SUPERVISOR MPU 8-SOIC
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 2,500
类型: 简单复位/加电复位
监视电压数目: 1
输出: 推挽式,图腾柱
复位: 低有效
复位超时: 最小为 140 ms
电压 - 阀值: 2.93V
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 8-SOIC(0.154",3.90mm 宽)
供应商设备封装: 8-SOIC
包装: 带卷 (TR)
MAX705–MAX708/MAX813L
Low-Cost, μP Supervisory Circuits
WDI
6
WATCHDOG
TRANSITION
DETECTOR
WATCHDOG
TIMER
8
WDO
V CC
8
RESET
MR
V CC
1
2
V CC
250 μ A
TIMEBASE FOR
RESET AND
WATCHDOG
RESET
GENERATOR
7
RESET
(RESET)
MR
V CC
1
2
250 μ A
RESET
GENERATOR
7
RESET
MAX705
4.65V*
MAX707
MAX708
PFI
4
4.65V*
MAX706
MAX813L
5
PFO
PFI
4
5
PFO
1.25V
1.25V
3
GND
* 4.40V FOR MAX7O6.
3
GND
* 4.40V FOR MAX7O6.
( ) ARE FOR MAX813L ONLY.
Figure 1. MAX705/MAX706/MAX813L Block Diagram
_______________Detailed Description
Reset Output
A microprocessor’s (μP’s) reset input starts the μP in a
known state. Whenever the μP is in an unknown state, it
should be held in reset. The MAX705-MAX708/MAX813L
assert reset during power-up and prevent code execu-
tion errors during power-down or brownout conditions.
On power-up, once V CC reaches 1V, RESET is a guaran-
teed logic low of 0.4V or less. As V CC rises, RESET stays
low. When V CC rises above the reset threshold, an inter-
nal timer releases RESET after about 200ms. RESET puls-
es low whenever V CC dips below the reset threshold, i.e.
brownout condition. If brownout occurs in the middle of
a previously initiated reset pulse, the pulse continues for
at least another 140ms. On power-down, once V CC falls
below the reset threshold, RESET stays low and is guar-
anteed to be 0.4V or less until V CC drops below 1V.
The MAX707/MAX708/MAX813L active-high RESET output
is simply the complement of the RESET output, and is
guaranteed to be valid with V CC down to 1.1V. Some μPs,
such as Intel’s 80C51, require an active-high reset pulse.
Watchdog Timer
The MAX705/MAX706/MAX813L watchdog circuit moni-
tors the μP’s activity. If the μP does not toggle the watch-
dog input (WDI) within 1.6sec and WDI is not three-stat-
ed, WDO goes low. As long as RESET is asserted or the
6
Figure 2. MAX707/MAX708 Block Diagram
WDI input is three-stated, the watchdog timer will stay
cleared and will not count. As soon as reset is released
and WDI is driven high or low, the timer will start counting.
Pulses as short as 50ns can be detected.
Typically, WDO will be connected to the non-maskable
interrupt input (NMI) of a μP. When V CC drops below
the reset threshold, WDO will go low whether or not the
watchdog timer has timed out yet. Normally this would
trigger an NMI interrupt, but RESET goes low simultane-
ously, and thus overrides the NMI interrupt.
If WDI is left unconnected, WDO can be used as a low-
line output. Since floating WDI disables the internal
timer, WDO goes low only when V CC falls below the
reset threshold, thus functioning as a low-line output.
The MAX705/MAX706 have a watchdog timer and a
RESET output. The MAX707/MAX708 have both active-
high and active-low reset outputs. The MAX813L has
both an active-high reset output and a watchdog timer.
Manual Reset
The manual-reset input ( MR ) allows reset to be triggered
by a pushbutton switch. The switch is effectively
debounced by the 140ms minimum reset pulse width.
MR is TTL/CMOS logic compatible, so it can be driven by
an external logic line. MR can be used to force a watch-
dog timeout to generate a reset pulse in the MAX705/
MAX706/MAX813L. Simply connect WDO to MR .
Maxim Integrated
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