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参数资料
| 型号： | MAX7302ATE+T |
| 厂商： | Maxim Integrated |
| 文件页数： | 3/30页 |
| 文件大小： | 0K |
| 描述： | IC LED DRIVER LINEAR 16-TQFN |
| 产品培训模块： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 标准包装： | 2,500 |
| 拓扑： | 开路漏极，PWM |
| 输出数： | 9 |
| 内部驱动器： | 是 |
| 类型 - 主要： | 背光，LED 闪烁器 |
| 类型 - 次要： | 白色 LED |
| 频率： | 1MHz |
| 电源电压： | 1.62 V ~ 3.6 V |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 16-WFQFN 裸露焊盘 |
| 供应商设备封装： | 16-TQFN（3x3） |
| 包装： | 带卷 (TR) |
| 工作温度： | -40°C ~ 125°C |
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SMBus/I 2 C Interfaced 9-Port,
Level-Translating GPIO and LED Driver with CLA
PORT, INTERRUPT ( INT ), AND RESET ( RST ) TIMING CHARACTERISTICS
(V DD = 1.62V to 3.6V, T A = T MIN to T MAX , unless otherwise noted. Typical values are at V DD = 3.3V, V LA = 3.3V, T A = +25°C.) (Note 1)
(Figures 10, 15, 16 and 17)
PARAMETER
Oscillator Frequency
SYMBOL
f CLK
CONDITIONS
f CLK = internal oscillator
f CLK = OSCIN external input
MIN
TYP
32
MAX
1
UNITS
kHz
MHz
Port Output Data Valid High Time
Port Output Data Valid Low Time (Note 6)
Port Input Setup Time
Port Input Hold Time
CLA Rise Time P5, P9 as Push-Pull Outputs
CLA Fall Time P5, P9 as Push-Pull Outputs
t PPVH
t PPVL
t PSU
t PH
t RFCLA
C L ≤ 100pF
C L ≤ 100pF (Note 2)
C L = 100pF
C L = 100pF
C L = 100pF, V LA ≥ 2.7V
0
4
17
14
4
1/f CLK
μs
s
μs
μs
ns
CLA Propagation Delay P2, P3, or P4 to P5; P6, P7,
or P8 to P9
INT Input Data Valid Time
INT Reset Delay Time from Acknowledge
RST Rising to START Condition Setup Time
RST Pulse Width
t PDCLA
t IV
t IR
t RST
t W
C L = 100pF, V LA ≥ 2.7V
C L = 100pF
C L = 100pF
900
500
28
50
4
4
ns
μs
μs
ns
ns
SERIAL INTERFACE TIMING CHARACTERISTICS
(V DD = 1.62V to 3.6V, T A = T MIN to T MAX , unless otherwise noted. Typical values are at V DD = 3.3V, V LA = 3.3V, T A = +25°C.) (Note 1)
(Figure 10)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Serial-Clock Frequency
Bus Timeout
Bus Free Time Between a STOP and a START Condition
Hold Time, (Repeated) START Condition
Repeated START Condition Setup Time
STOP Condition Setup Time
f SCL
t TIMEOUT
t BUF
t HD,STA
t SU,STA
t SU,STO
1.3
0.6
0.6
0.6
31
400
kHz
ms
μs
μs
μs
μs
Data Hold Time
Data Setup Time
SCL Clock Low Period
SCL Clock High Period
t HD,DAT
t SU,DAT
t LOW
t HIGH
(Note 3)
100
1.3
0.7
0.9
μs
ns
μs
μs
Rise Time of Both SDA and SCL Signals, Receiving
Fall Time of Both SDA and SCL Signals, Receiving
Fall Time of SDA Transmitting
t R
t F
t F.TX
(Notes 2, 4)
(Notes 2, 4)
(Note 4)
20 + 0.1C b
20 + 0.1C b
20 + 0.1C b
300
300
250
ns
ns
ns
Pulse Width of Spike Suppressed
Capacitive Load for Each Bus Line
t SP
C b
(Note 5)
(Note 2)
50
400
ns
pF
Note 1: All parameters are tested at T A = +25°C. Specifications over temperature are guaranteed by design.
Note 2: Guaranteed by design.
Note 3: A master device must provide a hold time of at least 300ns for the SDA signal (referred to V IL of the SCL signal) to bridge the
undefined region of SCL’s falling edge.
Note 4: C b = total capacitance of one bus line in pF. t R and t F are measured between 0.3 x V DD and 0.7 x V DD .
Note 5: Input filters on the SDA and SCL inputs suppress noise spikes less than 50ns.
Note 6: A startup time is required for the internal oscilator to start if it is not running already.
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