参数资料
型号: MAX7314ATG+T
厂商: Maxim Integrated Products
文件页数: 7/25页
文件大小: 0K
描述: IC I/O EXPANDER I2C 16B 24TQFN
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 2,500
接口: I²C
输入/输出数: 18
中断输出:
频率 - 时钟: 400kHz
电源电压: 2 V ~ 3.6 V
工作温度: -40°C ~ 125°C
安装类型: 表面贴装
封装/外壳: 24-WFQFN 裸露焊盘
供应商设备封装: 24-TQFN-EP(4x4)
包装: 带卷 (TR)
Reading a blink phase register reads the value stored
in the register, not the actual port condition. The port
output itself may or may not be at a valid logic level,
depending on the external load connected.
The 17th output, O16, is controlled through 2 bits in the
configuration register, which provide the same static or
blink control as the other 16 output ports.
PWM Intensity Control
The MAX7314 includes an internal oscillator, nominally
32kHz, to generate PWM timing for LED intensity con-
trol or other applications such as PWM trim DACs.
PWM can be disabled entirely for all the outputs. In this
case, all outputs are static and the MAX7314 operating
current is lowest because the internal PWM oscillator is
turned off.
The MAX7314 can be configured to provide any combi-
nation of PWM outputs and glitch-free logic outputs.
Each PWM output has an individual 4-bit intensity con-
trol (Table 14). When all outputs are to be used with the
same PWM setting, the outputs can be controlled
together instead using the global intensity control
(Table 13). Table 10 shows how to set up the MAX7314
to suit a particular application.
PWM Timing
The PWM control uses a 240-step PWM period, divided
into 15 master intensity timeslots. Each master intensity
timeslot is divided further into 16 PWM cycles (Figure 12).
The master intensity operates as a gate, allowing the indi-
vidual output settings to be enabled from 1 to 15 timeslots
per PWM period (Figures 13, 14, 15) (Table 13).
MAX7314
18-Port GPIO with LED Intensity Control,
Interrupt, and Hot-Insertion Protection
______________________________________________________________________________________
15
Table 5. Ports Configuration Registers
REGISTER DATA
REGISTER
R/
W
ADDRESS
CODE
(hex)
D7
D6
D5
D4
D3
D2
D1
D0
Ports configuration P7–P0
(1 = input, 0 = output)
0
Read back ports configuration P7–P0
1
0x06
OP7
OP6
OP5
OP4
OP3
OP2
OP1
OP0
Ports configuration P15–P8
(1 = input, 0 = output)
0
Read back ports configuration P15–P8
1
0x07
OP15
OP14
OP13
OP12
OP11
OP10
OP9
OP8
Table 6. Input Ports Registers
REGISTER DATA
REGISTER
R/
W
ADDRESS
CODE
(hex)
D7
D6
D5
D4
D3
D2
D1
D0
Read input ports P7–P0
1
0x00
IP7
IP6
IP5
IP4
IP3
IP2
IP1
IP0
Read input ports P15–P8
1
0x01
IP15
IP14
IP13
IP12
IP11
IP10
IP9
IP8
Table 7. Blink Logic
BLINK ENABLE
FLAG E
BLINK FLIP
FLAG B
BLINK INPUT
PIN
BLINK FLIP FLAG
EXOR
BLINK INPUT PIN
BLINK FUNCTION
OUTPUT REGISTERS USED
0
X
Disabled
Blink phase 0 registers
0
Blink phase 0 registers
0
1
Blink phase 1 registers
1
0
1
Blink phase 1 registers
1
11
0
Enabled
Blink phase 0 registers
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