参数资料
型号: MAX7318AUG+T
厂商: Maxim Integrated Products
文件页数: 17/19页
文件大小: 0K
描述: IC I/O EXPANDER I2C 16B 24TSSOP
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 2,500
接口: I²C,SM 总线
输入/输出数: 16
中断输出:
频率 - 时钟: 400kHz
电源电压: 2 V ~ 5.5 V
工作温度: -40°C ~ 125°C
安装类型: 表面贴装
封装/外壳: 24-TSSOP(0.173",4.40mm 宽)
供应商设备封装: 24-TSSOP
包装: 带卷 (TR)
包括: POR
Each transmission consists of a START condition sent by
a master, followed by the MAX7318 7-bit slave address
plus R/
W bit, a register address byte, 1 or more data
bytes, and finally a STOP condition (Figure 3).
START and STOP Conditions
Both SCL and SDA remain high when the interface is
not busy. A master signals the beginning of a transmis-
sion with a START (S) condition by transitioning SDA
from high to low while SCL is high. When the master
has finished communicating with the slave, it issues a
STOP (P) condition by transitioning SDA from low to
high while SCL is high. The bus is then free for another
transmission (Figure 3).
Bit Transfer
One data bit is transferred during each clock pulse.
The data on SDA must remain stable while SCL is high
(Figure 4).
Acknowledge
The acknowledge bit is a clocked 9th bit, which the
recipient uses as a handshake receipt of each byte of
data (Figure 5). Thus, each byte transferred effectively
requires 9 bits. The master generates the 9th clock
pulse, and the recipient pulls down SDA during the
acknowledge clock pulse, such that the SDA line is sta-
ble low during the high period of the clock pulse. When
the master is transmitting to the MAX7318, the MAX7318
MAX7318
2-Wire-Interfaced, 16-Bit, I/O Port Expander
with Interrupt and Hot-Insertion Protection
_______________________________________________________________________________________
7
SDA
SCL
S
START
CONDITION
P
STOP
CONDITION
Figure 3. START and STOP Conditions
SDA
SCL
DATA LINE STABLE; DATA VALID CHANGE OF DATA ALLOWED
Figure 4. Bit Transfer
SCL
SDA
BY TRANSMITTER
CLOCK PULSE FOR ACKNOWLEDGMENT
START CONDITION
SDA
BY RECEIVER
12
8
9
S
Figure 5. Acknowledge
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