参数资料
型号: MAX7321AEE+
厂商: Maxim Integrated Products
文件页数: 13/15页
文件大小: 0K
描述: IC I/O EXPANDER I2C 8B 16QSOP
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 100
接口: I²C
输入/输出数: 8
中断输出:
频率 - 时钟: 400kHz
电源电压: 1.71 V ~ 5.5 V
工作温度: -40°C ~ 125°C
安装类型: 表面贴装
封装/外壳: 16-SSOP(0.154",3.90mm 宽)
供应商设备封装: 16-QSOP
包装: 管件
包括: POR
MAX7321
I2C Port Expander with 8 Open-Drain I/Os
7
Maxim Integrated
RST Input
The RST input voids any I2C transaction involving the
MAX7321, forcing the MAX7321 into the I2C STOP con-
dition. A reset does not affect the interrupt output (INT).
Standby Mode
When the serial interface is idle, the MAX7321 automat-
ically enters standby mode, drawing minimal supply
current.
Slave Address, Power-Up Default Logic
Levels, and Input Pullup Selection
Address inputs AD0 and AD2 determine the MAX7321
slave address, set the power-up I/O state for the ports,
and select which inputs have pullup resistors. Internal
pullups and power-up default states are set in groups
of four (Table 3). The MAX7319, MAX7321, MAX7322,
and MAX7323 use a different range of slave addresses
(110xxxx) than the MAX7320 (101xxxx) (Table 2).
The MAX7321 slave address is determined on each I2C
transmission, regardless of whether the transmission is
actually addressing the MAX7321. The MAX7321 distin-
guishes whether address inputs AD2 and AD0 are con-
nected to SDA or SCL instead of fixed logic levels V+ or
GND during this transmission. This means that the
MAX7321 slave address can be configured dynamical-
ly in the application without cycling the device supply.
On initial power-up, the MAX7321 cannot decode
address inputs AD0 and AD2 fully until the first I2C
transmission. AD0 and AD2 initially appear to be con-
nected to V+ or GND. This is important because the
address selection is used to determine the power-up
logic state and whether pullups are enabled. However,
at power-up, the I2C SDA and SCL bus interface lines
are high impedance at the pins of every device (master
or slave) connected to the bus, including the MAX7321.
This is guaranteed as part of the I2C specification.
Therefore, address inputs AD2 and AD0 that are con-
nected to SDA or SCL normally appear at power-up to
be connected to V+. The power-up logic uses AD0 to
select the power-up state and whether pullups are
enabled for ports P3–P0, and AD2 for ports P7–P4. The
rule is that a logic-high, SDA, or SCL connection
selects the pullups and sets the default logic state to
high. A logic-low deselects the pullups and sets the
default logic state to low (Table 3). The port configura-
tion is correct on power-up for a standard I2C configu-
ration, where SDA or SCL are pulled up to V+ by the
external I2C pullup resistors.
PART
I2C SLAVE
ADDRESS
INPUTS
INTERRUPT
MASK
OPEN-
DRAIN
OUTPUTS
PUSH-
PULL
OUTPUTS
I2C DATA WRITE
I2C DATA READ
MAX7319
110xxxx
8
Yes
<I7–I0 interrupt
mask>
<I7–I0 port inputs>
<I7–I0 transition flags>
MAX7320
101xxxx
8
<O7–O0 port
outputs>
<O7-O0 port inputs>
MAX7321
110xxxx
Up to 8
Up to 8
<P7–P0 port
outputs>
<P7–P0 port inputs>
<P7–P0 transition flags>
MAX7322
110xxxx
4
Yes
4
<O7, O6 outputs,
I5–I2 interrupt
mask, O1, O0
outputs>
<O7, O6, I5–I2, O1, O0 port
inputs>
<0, 0, I5–I2 transition flags,
0, 0>
MAX7323
110xxxx
Up to 4
Up to 4
4
<port outputs>
<O7, O6, P5–P2, O1, O0 port
inputs>
<0, 0, P5–P2 transition flags,
0, 0>
MAX7328
0100xxx
Up to 8
Up to 8
<P7–P0 port
outputs>
<P7–P0 port inputs>
MAX7329
0111xxx
Up to 8
Up to 8
<P7–P0 port
outputs>
<P7–P0 port inputs>
Table 2. Read and Write Access to Eight-Port Expander Family
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