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参数资料
| 型号： | MAX7329AWE+T |
| 厂商： | Maxim Integrated Products |
| 文件页数： | 7/13页 |
| 文件大小： | 0K |
| 描述： | IC I/O EXPANDER I2C 8B 16SOIC |
| 产品培训模块： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 标准包装： | 1,000 |
| 接口： | I²C |
| 输入/输出数： | 8 |
| 中断输出： | 是 |
| 频率 - 时钟： | 100kHz |
| 电源电压： | 2.5 V ~ 5.5 V |
| 工作温度： | -40°C ~ 125°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 16-SOIC（0.295"，7.50mm 宽） |
| 供应商设备封装： | 16-SOIC W |
| 包装： | 带卷 (TR) |
MAX7328/MAX7329
I2C Port Expanders with Eight I/O Ports
_______________________________________________________________________________________
3
Note 1: All parameters are tested at TA = +25°C. Specifications over temperature are guaranteed by design.
Note 2: Guaranteed by design.
Note 3: A master device must provide a hold time of at least 300ns for the SDA signal (referred to VIL of the SCL signal) to bridge
the undefined region of SCL’s falling edge.
PORT AND INTERRUPT INT TIMING CHARACTERISTICS
(Typical Operating Circuit, V+ = 2.5V to 5.5V, TA = TMIN to TMAX, unless otherwise noted. Typical values are at V+ = 5V, TA = +25°C.)
(Note 1)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Port Output Data Valid
tPPV
CL
≤ 100pF
4
s
Port Input Setup Time
tPSU
CL
≤ 100pF
0
s
Port Input Hold Time
tPH
CL
≤ 100pF
4
s
INT Input Data Valid Time
tIV
CL
≤ 100pF
4
s
INT Reset Delay Time from
Acknowledge
tIR
CL
≤ 100pF
4
s
TIMING CHARACTERISTICS
(Typical Operating Circuit, V+ = 2.5V to 5.5V, TA = TMIN to TMAX, unless otherwise noted. Typical values are at V+ = 5V, TA = +25°C.)
(Note 1)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Serial Clock Frequency
fSCL
100
kHz
Tolerable Spike Width on Bus
tSP
(Note 2)
100
ns
Bus Free Time between STOP
and START
tBUF
4.7
s
START or Repeated START Setup
Time
tSU, STA
4.7
s
START or Repeated START Hold
Time
tHD, STA
4s
SCL Clock Low Period
tLOW
4.7
s
SCL Clock High Period
tHIGH
4s
SDA and SCL Rise Time
tR
(Note 2)
1
s
SDA and SCL Fall Time
tF
(Note 2)
300
ns
Data Setup Time
tSU, DAT
250
ns
Data Hold Time
tHD, DAT
(Note 3)
0.9
s
SCL Low to Data-Out Valid
tVD, DAT
SCL low to SDA output valid
3.4
s
STOP Condition Setup Time
tSU, STO
4s
Capacitive Load for Each Bus Line
Cb
(Note 2)
400
pF
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