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参数资料
| 型号： | MAX7391APVB |
| 厂商： | MAXIM INTEGRATED PRODUCTS INC |
| 元件分类： | 时钟产生/分配 |
| 英文描述： | 12 MHz, OTHER CLOCK GENERATOR, PDSO8 |
| 封装： | MO-187C-AA, MICRO, SOP-8 |
| 文件页数： | 10/12页 |
| 文件大小： | 594K |
| 代理商： | MAX7391APVB |
MAX7391
Speed-Switching Clock Generator
with Power Fail
_______________________________________________________________________________________
7
Low-Voltage Lockout
The reset output asserts whenever VCC drops below the
reset falling threshold, VTH-. The difference between the
reset rising and falling threshold values is VTH+ - (VTH-).
The nominal hysteresis value is 2% of the reset rising
threshold value. The reset detection circuitry provides
filtering to prevent triggering on negative voltage spikes.
See the Typical Operating Characteristics for a plot of
maximum transient duration without causing a reset
pulse vs. reset comparator overdrive.
Figure 1 shows the reset output (RST/RST) behavior
during power-up and brownout.
Power Fail
The power-fail function provides early warning of a power
failure. The power-fail comparator detects the condition
of either an external voltage or the VCC supply voltage.
Internal (VCC) detection is configured by connecting
PFI to VCC. The internal VCC rising threshold (VITH) is
set at 4.38V. The open-drain PFO asserts low if the VCC
supply voltage drops below the VCC falling threshold
value (VIHYST). The VCC falling threshold is nominally
2% below the VCC rising threshold.
External power-fail detection is selected when the
applied voltage on PFI (VPFI) is less than 0.65 x VCC
(VSEL minimum). When the voltage on PFI is more than
0.85 x VCC (VSEL maximum), the device switches to
internal monitoring. External power-fail detection is nor-
mally used with a resistive divider from the supply
being monitored. See the Typical Application Circuit.
For a 3.3V supply, the voltage on PFI needs to be set
externally and less than 0.65 x VCC (VSEL minimum). To set
the voltage on PFI externally, choose R1 and R2 so that:
See Figure 1 for PFO behavior during power-up and
brownout.
VPFI =
×
+
R
PowerSupply
RR
2
21
5
4
3
2
1
CLK
tRST
VTH+
VITH
VTH-
VCCR
VITH - VIHYST
RST
PFO
CLOCK STARTS ON INTERNAL
POR (VTH+, VCC RISING).
RST RELEASES AFTER THE
RESET TIMEOUT PERIOD.
V
CC
(V)
PFO ASSERTS AS VCC DROPS
BELOW VTH. CLOCK FREQUENCY
REDUCTION SHOWN IS ACHIEVED
BY CONNECTING SPEED TO PFO.
RST CONTINUES TO
ASSERT UNTIL VCCR.
RST ASSERTS ON RESET FALLING
VOLTAGE (VTH-, VCC FALLING).
CLOCK STOPS.
Figure 1. RST/RST and PFO Behavior During Power-Up and Brownout
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相关代理商/技术参数 |
参数描述 |
|---|---|
| MAX7391CMAC | 功能描述:时钟发生器及支持产品 RoHS:否 制造商:Silicon Labs 类型:Clock Generators 最大输入频率:14.318 MHz 最大输出频率:166 MHz 输出端数量:16 占空比 - 最大:55 % 工作电源电压:3.3 V 工作电源电流:1 mA 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:QFN-56 |
| MAX7391CMRD | 功能描述:时钟发生器及支持产品 RoHS:否 制造商:Silicon Labs 类型:Clock Generators 最大输入频率:14.318 MHz 最大输出频率:166 MHz 输出端数量:16 占空比 - 最大:55 % 工作电源电压:3.3 V 工作电源电流:1 mA 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:QFN-56 |
| MAX7391CMRD-T | 制造商:Maxim Integrated Products 功能描述:SPEED-SWITCHING CLOCK GENERATOR WIT - Tape and Reel |
| MAX7391CMTP | 功能描述:时钟发生器及支持产品 RoHS:否 制造商:Silicon Labs 类型:Clock Generators 最大输入频率:14.318 MHz 最大输出频率:166 MHz 输出端数量:16 占空比 - 最大:55 % 工作电源电压:3.3 V 工作电源电流:1 mA 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:QFN-56 |
| MAX7391CMTP-T | 功能描述:时钟发生器及支持产品 RoHS:否 制造商:Silicon Labs 类型:Clock Generators 最大输入频率:14.318 MHz 最大输出频率:166 MHz 输出端数量:16 占空比 - 最大:55 % 工作电源电压:3.3 V 工作电源电流:1 mA 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:QFN-56 |
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