参数资料
型号: MAX7456EUI+T
厂商: Maxim Integrated Products
文件页数: 27/44页
文件大小: 0K
描述: IC DISPLAY 1CH W/EEPROM 28TSSOP
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 2,500
类型: OSD(屏幕显示)视频发生器
应用: 安全系统,视频路由
安装类型: 表面贴装
封装/外壳: 28-SOIC(0.173",4.40mm 宽)裸露焊盘
供应商设备封装: 28-TSSOP 裸露焊盘
包装: 带卷 (TR)
Single-Channel Monochrome On-Screen
Display with Integrated EEPROM
Character Memory Mode Register (CMM)
Write address = 08H, read address = 88H.
Read/write access: unrestricted.
To write to this register, the following conditions must
be met:
1) STAT[5] = 0, the character memory (NVM) is not
busy.
2) VM0[3] = 0, the OSD is disabled.
X = Don’t care.
BIT
DEFAULT
FUNCTION
7–0
0000 0000
Only whole characters (54 bytes) can be written to or read from the nonvolatile character memory
(NVM) at one time. This is done through the (64 byte) shadow RAM (Figure 13). The shadow RAM is
accessed through the SPI port one byte at a time. The shadow RAM is written to and read from
NVM by the following procedures:
Writing to NVM
1010 XXXX = Write to NVM array from shadow RAM.
The 64 bytes from shadow RAM are written to the NVM array at the character-memory address
location (CMAH, CMAL) (Figure 13). The character memory is busy for approximately 12ms during
this operation. During this time, STAT[5] is automatically set to 1. The Character Memory Mode
register is cleared and STAT[5] is reset to 0 after the write operation has been completed. The user
does not need to write zeros afterwards.
Reading from NVM
0101 XXXX = Read from NVM array into shadow RAM.
The 64 bytes corresponding to the character-memory address (CMAH, CMAL) are read from the
NVM array into the shadow RAM (Figure 13). The character memory is busy for approximately 0.5s
during this operation. The CMM register is cleared after the operation is completed. The user does
not need to write zeros afterwards. During this time, STAT[5] is automatically set to 1. STAT[5] is
reset to 0 when the read operation has been complete.
If the display has been enabled (VM0[3] = 1) or the character memory is busy (STAT[5] = 1), NVM
read/write operation commands are ignored and the corresponding registers are not updated.
However, all the registers can be read at any time.
For all the character-memory operations, the character address is formed with Character Memory
Address High (CMAH[7:0]) and Character Memory Address Low (CMAL[7:0]) register bits (Figures
11, 12, and 13).
MAX7456
Maxim Integrated
33
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