参数资料
型号: MAX769EEI+T
厂商: Maxim Integrated Products
文件页数: 14/16页
文件大小: 0K
描述: IC PAGER SYSTEM 28-QSOP
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 2,500
应用: 手持/移动设备
电流 - 电源: 4µA
电源电压: 1.5 V ~ 5.5 V
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 28-QSOP
供应商设备封装: 28-QSOP
包装: 带卷 (TR)
2 or 3-Cell, Step-Up/Down,
Two-Way Pager System IC
Serial data is clocked in and out MSB first. Input data is
latched on the CLK rising edge, and output data is
shifted out on the CLK falling edge. When CS goes low,
DO immediately contains the MSB output bit (D7). D6 is
not clocked out until the falling clock edge that follows
the first rising clock edge after a Chip Select. See the
timing diagrams in Figures 4 and 5.
SPI writes and reads concurrently, so it may be neces-
sary to perform dummy writes in order to read output
data. Four output data bits (D7–D4, Table 4) are sent
from SDO each time a serial operation occurs.
CS
???
When R2 = 0, R0 and R1 are address pointers.
However, when R2 = 1, the 7 remaining bits (R1, R0
and D4–D0) become DAC programming bits. This vio-
lation of programming etiquette (R1 and R0 are some-
times address bits and other times data bits) allows the
CH DAC to be loaded with only one write operation.
Writing all zeros to the CH DAC turns it, the CH0, CH1,
and CH2 comparators, and the NICD and BATT volt-
age-sensing resistors off to minimize current consump-
tion. This reduces current drain from OUT by about
30μA.
t CSH
t CSS
t CL
t CH
t CSH
SCLK
DIN
t DS
t DH
???
???
t DV
DOUT
Figure 4. Detailed Serial-Interface Timing
CS
SCL
???
t DO
t TR
SCO
SDI
D7
R2
D6
R1
D5
R0
D4
D4
0
D3
0
D2
0
D1
0
D0
Figure 5. CS , SCL, SDO, and SDI Serial Timing
14
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