参数资料
型号: MAX7705CSA+T
厂商: Maxim Integrated Products
文件页数: 4/8页
文件大小: 0K
描述: IC MPU SUPPLY MON 8-SOIC
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 2,500
类型: 简单复位/加电复位
监视电压数目: 1
输出: 推挽式,图腾柱
复位: 低有效
复位超时: 最小为 140 ms
电压 - 阀值: 4.65V
工作温度: 0°C ~ 70°C
安装类型: 表面贴装
封装/外壳: 8-SOIC(0.154",3.90mm 宽)
供应商设备封装: 8-SOIC
包装: 带卷 (TR)
μP Power-Supply Monitor
with Reset
150
100
T A = +25°C
mum pulse width a negative-going V CC transient may
have without causing a reset pulse to be issued. As
the magnitude of the transient increases (goes farther
below the reset threshold), the maximum allowable
pulse width decreases. Typically, a V CC transient that
goes 100mV below the reset threshold and lasts 40μs
or less will not cause a reset pulse to be issued.
A 0.1μF bypass capacitor mounted as close as possible
50
10ns
0
10 100 1k 10k
RESET COMPARATOR OVERDRIVE, V TH - V CC (mV)
Figure 1. Maximum Transient Duration without Causing a
Reset Pulse vs. Reset Comparator Overdrive
__________Applications Information
Replacing the TL7705 with a MAX7705
in an Existing Design
The MAX7705 has only three active pins: V CC , GND,
and RESET . When using a TL7705 with a μP that has
a RESET input, simply plug the MAX7705 into the
same socket and omit the RESET pull-up resistor, reset
timing capacitor, and reference bypass capacitor (see
the Typical Operating Circuit).
The MAX7705 monitors the V CC voltage and asserts
reset whenever V CC falls below the reset threshold.
The reset power-up delay is created by an internal
fixed oscillator. This delay is 100% tested and guaran-
teed over the full temperature range. The RESET out-
put both sources and sinks current (see RESET Output
Voltage in the Electrical Characteristics).
Negative-Going V CC Transients
The MAX7705 asserts RESET during power-up,
power-down, and brownout conditions. However, it is
relatively immune to short-duration negative-going V CC
transients (glitches).
Figure 1 shows typical transient duration vs. reset com-
parator overdrive for which the MAX7705 does not gen-
erate a reset pulse. The graph was generated using a
fast-edge, negative-going pulse applied to V CC , starting
1.5V above the actual reset threshold and ending below
the reset threshold by the magnitude indicated (reset
comparator overdrive). It indicates the typical maxi-
to pin 2 (V CC ) provides additional transient immunity.
Ensuring a Valid RESET Output
Down to V CC = 0V
When V CC falls below 1V, the MAX7705 RESET output
no longer sinks current; it becomes high impedance.
Therefore, high-impedance CMOS logic inputs con-
nected to the RESET output can drift to indeterminate
voltages. In most applications this presents no prob-
lem, as μP and other circuitry is generally inoperative
with V CC below 1V. In applications where the RESET
output must be valid down to 0V, adding a pull-down
resistor to the RESET pin (as shown in Figure 2) will
cause any stray leakage currents to flow to ground,
holding RESET low. The resistance value of R1 is not
critical. It should be about 100k ? , which is large
enough not to load RESET and small enough to pull
RESET to ground.
V CC
MAX7705
RESET
R1
GND
Figure 2. RESET Valid to V CC = Ground Circuit
4
_______________________________________________________________________________________
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