参数资料
型号: MAX791ESE+T
厂商: Maxim Integrated Products
文件页数: 7/19页
文件大小: 0K
描述: IC SUPERVISOR MPU 16-SOIC
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 2,500
类型: 备用电池电路
监视电压数目: 1
输出: 推挽式,图腾柱
复位: 低有效
复位超时: 最小为 140 ms
电压 - 阀值: 4.65V
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 16-SOIC(0.154",3.90mm 宽)
供应商设备封装: 16-SOIC
包装: 带卷 (TR)
Microprocessor Supervisory Circuit
Pin Description
– — — –
– — — — — –
Chip-Enable Output. C E OUT goes low only when C E IN is low and V CC is above the reset threshold. If C E IN is
– — — — –
– — — –
PIN
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
NAME
VBATT
V OUT
V CC
GND
BATT ON
– — — –
P F O
PFI
SWT
– — –
M R
– –
— — — — —
L O W L I N E
WDI
– — –
C E OUT
– — –
C E IN
– — — –
W D O
– — — — — –
R E S E T
– — — — –
W D P O
FUNCTION
Backup-Battery Input. Connect to external battery or capacitor and charging circuit.
Output Supply Voltage. V OUT connects to V CC when V CC is greater than VBATT and V CC is above the reset
threshold. When V CC falls below VBATT and V CC is below the reset threshold, V OUT connects to VBATT.
Connect a 0.1μF capacitor from V OUT to GND.
Input Supply Voltage—+5V input
Ground. 0V reference for all signals.
Battery-On Output. Goes high when V OUT switches to VBATT. Goes low when V OUT switches to V CC . Connect
the base of a PNP through a current-limiting resistor to BATT ON for V OUT current requirements greater than
250mA.
– — — –
Power-Fail Output. This is the output of the power-fail comparator. P F O goes low when PFI is less than 1.25V.
This is an uncommitted comparator, and has no effect on any other internal circuitry.
Power-Fail Input. This is the noninverting input to the power-fail comparator. When PFI is less than 1.25V,
P F O goes low. Connect PFI to GND or V OUT when not used.
Set Watchdog-Timeout Input. Connect this input to V OUT to select the default 1.6s watchdog-timeout period.
Connect a capacitor between this input and GND to select another watchdog-timeout period. Watchdog-timeout
period = 2.1 x (capacitor value in nF) ms.
Manual-Reset Input. This input can be tied to an external momentary pushbutton switch, or to a logic gate out-
– –
– — – —
– –
put. R E S E T remains low as long as M R is held low and for 200ms after M R returns high.
— — — — —
L O W L I N E Output goes low when V CC falls to 150mV above the reset threshold. The output can be used to gen-
erate an NMI if the unregulated supply is inaccessible.
– — — – – — — –
Watchdog Input. WDI is a three-level input. If WDI remains either high or low for longer than the watchdog time-
out period, W D O goes low. W D O remains low until the next transition at WDI. Leaving WDI unconnected disables
the watchdog function. WDI connects to an internal voltage-divider between V OUT and GND, which sets it to mid-
supply when left unconnected.
– – – – – –
— — —
– – – –
— —
low when reset is asserted, C E OUT will stay low for 15μs or until C E IN goes high, whichever occurs first.
Chip-Enable Input. The input to chip-enable gating circuit. Connect to GND or V OUT if not used.
– — — –
– — — – – — — – – — — –
– — — — — –
Watchdog Output. W D O goes low if WDI remains either high or low longer than the watchdog-timeout period.
W D O returns high on the next transition at WDI. W D O remains high if WDI is unconnected. W D O is also high
when R E S E T is asserted.
– – – –
— — — — — — — —
R E S E T Output goes low whenever V CC falls below the reset threshold. R E S E T will remain low for typically 200ms
after V CC crosses the reset threshold on power-up.
– — — — –
Watchdog-Pulse Output. Upon the absence of a transition at WDI, W D P O will pulse low for a minimum of 1ms.
W D P O precedes W D O by 70ns.
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