参数资料
型号: MAX801LCSA+T
厂商: Maxim Integrated Products
文件页数: 8/12页
文件大小: 0K
描述: IC SUPERVISOR MPU 8-SOIC
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 2,500
类型: 备用电池电路
监视电压数目: 1
复位: 高有效/低有效
复位超时: 最小为 140 ms
电压 - 阀值: 4.675V
工作温度: 0°C ~ 70°C
安装类型: 表面贴装
封装/外壳: 8-SOIC(0.154",3.90mm 宽)
供应商设备封装: 8-SOIC
包装: 带卷 (TR)
8-Pin μP Supervisory Circuits
with ±1.5% Reset Accuracy
V CC
V RST V LL
V CC
V RST + V LR V RST
V LOWLINE
V LOWLINE
t LL
V RESET
V RESET
(MAX801)
t RP
t RP
V RESET
V RESET
(MAX801)
t RD
t RD
V CE OUT
(MAX808)
V BATT
V CE OUT
(MAX808)
t RCE
V BATT
SHOWN FOR V CC = 0V to 5V, V BATT = 2.8V, CE IN = GND
Figure 2a. Timing Diagram, V CC Rising
_______________Detailed Description
The MAX801/MAX808 microprocessor (μP) supervisory
circuits provide power-supply monitoring and backup-
battery switchover in μP systems. The MAX801 also
provides program-execution watchdog functions
(Figure 1). Use of BiCMOS technology results in an
improved, 1.5% reset-threshold precision while keeping
supply currents typically at 68μA (48μA for the
MAX808). The MAX801/MAX808 are intended for bat-
tery-powered applications that require high reset-
threshold precision, allowing a wide power-supply
operating range while preventing the system from oper-
ating below its specified voltage range.
RESET and RESET Outputs
The MAX801/MAX808’s RESET output ensures that the
μP powers up in a known state, and prevents code-
execution errors during power-down and brownout
conditions. It does this by resetting the μP, terminating
program execution when V CC dips below the reset
threshold. Each time RESET is asserted, it stays low for
at least the 200ms reset timeout period (set by an inter-
nal timer) to ensure the μP has adequate time to return
to an initial state. The internal timer restarts any time
V CC goes below the reset threshold (V RST ) before the
reset timeout period is completed. The watchdog timer
on the MAX801 can also initiate a reset (see the
MAX801 Watchdog Timer section).
SHOWN FOR V CC = 5V to 0V, V BATT = 2.8V, CE IN = GND
Figure 2b. Timing Diagram, V CC Falling
The RESET output is active low, and is implemented with
a strong pull-down/relatively weak pull-up structure. It is
guaranteed to be a logic low for 0V < V CC < V RST , pro-
vided V BATT is greater than 2V. Without a backup bat-
tery, RESET is guaranteed valid for V CC ≥ 1V.
The RESET output is the inverse of the RESET output; it
both sources and sinks current and cannot be wire-OR
connected.
Low-Line Comparator
The low-line comparator monitors V CC with a threshold
voltage typically 52mV above the reset threshold, with
13mV of hysteresis. Use LOWLINE to provide a non-
maskable interrupt (NMI) to the μP when power begins
to fall, initiating an orderly software shutdown routine. In
most battery-operated portable systems, reserve ener-
gy in the battery provides ample time to complete the
shutdown routine once the low-line warning is encoun-
tered and before reset asserts. If the system must con-
tend with a more rapid V CC fall time (such as when the
main battery is disconnected, when a DC-DC converter
shuts down, or when a high-side switch is opened dur-
ing normal operation), use capacitance on the V CC line
to provide time to execute the shutdown routine (Figure
3). First calculate the worst-case time required for the
system to perform its shutdown routine. Then, with
worst-case shutdown time, worst-case load current,
and minimum low-line to reset threshold (V LR(min) ),
8
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