参数资料
型号: MAX806RCSA+T
厂商: Maxim Integrated Products
文件页数: 9/12页
文件大小: 0K
描述: IC SUPERVISOR MPU 8-SOIC
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 2,500
类型: 备用电池电路
监视电压数目: 1
输出: 推挽式,图腾柱
复位: 低有效
复位超时: 最小为 140 ms
电压 - 阀值: 2.625V
工作温度: 0°C ~ 70°C
安装类型: 表面贴装
封装/外壳: 8-SOIC(0.154",3.90mm 宽)
供应商设备封装: 8-SOIC
包装: 带卷 (TR)
3.0V/3.3V Microprocessor Supervisory Circuits
3.0V OR 3.3V
+5V
V CC
MAX690T/S/R
MAX704T/S/R
V OUT
TO STATIC
RAM
3.0V OR
3.3V
V CC
MAX690T/S/R
MAX704T/S/R
V OUT
TO STATIC
RAM
1N4148
MAX802T/S/R
MAX804T/S/R
1N4148
MAX802T/S/R
MAX804T/S/R
0.47F
VBATT MAX805T/S/R RESET
MAX806T/S/R (RESET)
GND
TO μ P
0.47F
VBATT MAX805T/S/R RESET
MAX806T/S/R (RESET)
GND
TO μ P
a
( ) ARE FOR MAX804T/S/R, MAX805T/S/R ONLY
b
( ) ARE FOR MAX804T/S/R, MAX805T/S/R ONLY
Figure 3. Using a SuperCap as a Backup Power Source
result. To correct this, connect a 4.7k Ω resistor
– — — — — –
should be larger than 10k Ω so it does not load down the
– — — –
PFI. P F O can be used to generate – — – interrupt to the
– — — –
– — –
– — — –
– — — –
– — — — — –
Connecting an ordinary signal diode in series with R3,
as shown in Figure 4b, causes the lower trip point (V L )
to coincide with the trip point without hysteresis (V TRIP ),
so the entire hysteresis window occurs above V TRIP .
This method provides additional noise margin without
compromising the accuracy of the power-fail threshold
when the monitored voltage is falling. It is useful for
accurately detecting when a voltage falls past a
threshold.
The current through R1 and R2 should be at least 1μA to
ensure that the 25nA (max over extended temperature
range) PFI input current does not shift the trip point. R3
– — — –
P F O pin. Capacitor C1 adds additional noise rejection.
Monitoring an Additional Power Supply
These μP supervisors can monitor either positive or
negative supplies using a resistor voltage divider to
an
μP (Figure 5). Connecting P F O to M R on the MAX704
and MAX806 causes reset to assert when the
monitored supply goes out of tolerance. Reset remains
asserted as long as P F O holds M R low, and for 200ms
after P F O goes high.
Interfacing to μPs
with Bidirectional Reset Pins
μPs with bidirectional reset pins, such as the Motorola
68HC11 series, can contend with the MAX690_/
MAX704_/MAX802_/MAX806_ R E S E T output. If, for
– — — — — –
example, the R E S E T output is driven high and the μP
wants to pull it low, indeterminate logic levels may
– — — — — –
between the R E S E T output and the μP reset I/O, as in
Figure 6. Buffer the R E S E T output to other system
components.
Negative-Going V CC Transients
While issuing resets to the μP during power-up, power-
down, and brownout conditions, these supervisors are
relatively immune to short-duration negative-going V CC
transients (glitches). It is usually undesirable to reset
the μP when V CC experiences only small glitches.
Figure 7 shows maximum transient duration vs. reset-
comparator overdrive, for which reset pulses are not
generated. The graph was produced using negative-
going V CC pulses, starting at 3.3V and ending below
the reset threshold by the magnitude indicated (reset
comparator overdrive). The graph shows the maximum
pulse width a negative-going V CC transient may
typically have without causing a reset pulse to be
issued. As the amplitude of the transient increases
(i.e., goes farther below the reset threshold), the
maximum allowable pulse width decreases. Typically,
a V CC transient that goes 100mV below the reset
threshold and lasts for 40μs or less will not cause a
reset pulse to be issued.
A 100nF bypass capacitor mounted close to the V CC
pin provides additional transient immunity.
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