参数资料
型号: MAX835EUK+T
厂商: Maxim Integrated Products
文件页数: 6/9页
文件大小: 0K
描述: IC MONITOR VOLT LATCH SOT23-5
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 1
类型: 简单复位/加电复位
监视电压数目: 1
输出: 推挽式,图腾柱
复位: 低有效
复位超时: 标准传输延迟为 80 µs
电压 - 阀值: 可调节/可选择
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: SC-74A,SOT-753
供应商设备封装: SOT-23-5
包装: 标准包装
产品目录页面: 1414 (CN2011-ZH PDF)
其它名称: MAX835EUK+TDKR
Micropower, Latching Voltage Monitors
in SOT23-5
_______________Detailed Description
The MAX834/MAX835 micropower voltage monitors con-
tain a 1.204V precision bandgap reference and a com-
parator with an output latch (Figure 1). The difference
between the two parts is the structure of the comparator
output driver. The MAX834 has an open-drain, n-channel
output driver that can be pulled up to a voltage higher
than V CC , but less than 11V. The MAX835’s output is
push-pull and can both source and sink current.
Programming the Trip Voltage (V TRIP )
Two external resistors set the trip voltage, V TRIP (Figure 2).
V TRIP is the point at which the falling monitored voltage
(typically V CC ) causes OUT to go low. IN’s high input
impedance allows the use of large-value resistors without
compromising trip voltage accuracy. To minimize current
consumption, choose a value for R2 between 500k ? and
1M ? , then calculate R1 as follows:
R1 = R2 [(V TRIP / V TH ) - 1]
> V TRIP
V MON
< V TRIP
where V TRIP is the desired trip voltage and V TH is the
threshold voltage (1.204V). The voltage at IN must be at
least 1V less than V CC .
Latched-Output Operation
The MAX834/MAX835 feature a level-sensitive latch
input (CLEAR), designed to eliminate the need for hys-
teresis in battery undervoltage-detection applications.
When the monitored voltage (V MON ) is above the pro-
grammed trip voltage (V TRIP ) (as when the system bat-
tery is recharged or a fresh battery is installed), pulse
CLEAR low-high-low for at least 1μs to reset the output
latch ( OUT goes high). When V MON falls below V TRIP ,
OUT goes low and remains low (even if V MON rises
above V TRIP ), until CLEAR is pulsed high again with
V MON > V TRIP . Figure 3a shows the timing relationship
between V MON , OUT , and CLEAR.
V CC
CLEAR
0V
V CC
OUT
0V
Figure 3a. Timing Diagram
> V TRIP
V MON
< V TRIP
V CC
OUT
0V
Figure 3b. Timing Diagram, CLEAR = V CC
> 1 μ s
> 1 μ s
> 1 μ s
6
_______________________________________________________________________________________
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