参数资料
型号: MAX848ESE+T
厂商: Maxim Integrated Products
文件页数: 11/16页
文件大小: 0K
描述: IC DC-DC CONV LN HP 16-SOIC
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 2,500
应用: 转换器,RF 数据链路
输入电压: 0.7 V ~ 5.5 V
输出数: 1
输出电压: 3.3V,2.7 V ~ 5.5 V
工作温度: 0°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 16-SOIC(0.154",3.90mm 宽)
供应商设备封装: 16-SOIC
包装: 带卷 (TR)
1-Cell to 3-Cell, High-Power,
Low-Noise, Step-Up DC-DC Converters
POUT
P
OUT
OUTPUT
FEEDBACK
REF
R Q
LX
MAX848
MAX849
POKIN
R1
N
S
FB
R2
PGND
GND
POK
R3
PWM-MODE
CURRENT-
LIMIT LEVEL
OSC
Figure 4. Controller Block Diagram in PWM Mode
where V REF = 1.25V, V OUT is the desired output volt-
age, and V TRIP is the desired trip level for the power-
good comparator.
Figure 5. Adjustable Output Voltage and Power-Good Trip Level
AIN1
Power-OK
The MAX848/MAX849 feature a power-good compara-
AINSEL
C
C
tor. This comparator ’s open-drain output, POK, is
pulled low when the output voltage falls below the nom-
inal internal threshold level of 3V with POKIN = 0V. To
AIN2
set the power-good trip level externally, refer to the
Setting the Output Voltage Externally section.
Analog-to-Digital Converter (ADC)
2 x REF
C/2
REF
D
Q
The MAX848/MAX849 have an internal, two-channel, seri-
al ADC. The ADC converts an analog input voltage into a
digital stream available at the DATA pin. The converter
C/2
skips clock pulses in proportion to the input voltage.
Output format is a return-to-zero bit stream with a bit
OSC
÷ 2
DATA
duration of 1/f CLK . At zero-scale input voltage, all pulses
are skipped and DATA remains low; with a positive full-
scale input voltage, no pulses are skipped; and at mid-
scale, every other pulse is skipped. The ADC’s clock is
one-half of the externally applied clock signal or one-half
of the internal 300kHz clock available at LX. In PFM
mode, the converter is not active and DATA is driven low.
Channel 1, AIN1, has an input voltage range of 0.625V
to 1.875V and is selected when AINSEL is low. Channel
2, AIN2, accepts inputs in the 0V to 2.5V range and is
selected when AINSEL is pulled high (Figure 6).
The ADC is a switched-capacitor type; therefore, an
anti-aliasing filter might be required at the inputs. Insert
a 1k ? series resistor and a 0.01μF filter capacitor in
noisy environments.
Figure 6. A/D Converter Block Diagram
Timer Function Implementation
Implement the necessary counter functions either with
discrete hardware or with microcontroller (μC) imple-
mentations. The output resolution depends on how
many of the ADC clock pulses are counted, as shown
in Figure 7.
Hardware Implementation
A complete hardware solution can be implemented
using either two counters or an ASIC. Resolution
depends on how many pulses are counted. The main
advantage of the discrete hardware implementation is
that accuracy is not affected by interrupt latency asso-
ciated with the μC solution.
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11
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