参数资料
型号: MAX8559EBAJJ+T
厂商: Maxim Integrated
文件页数: 8/12页
文件大小: 0K
描述: IC REG LDO 2.85V .3A 8-UCSP
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 2,500
稳压器拓扑结构: 正,固定式
输出电压: 2.85V
输入电压: 最高 6.5V
电压 - 压降(标准): 0.06V @ 100mA
稳压器数量: 2
电流 - 输出: 300mA(最小)
电流 - 限制(最小): 310mA
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 8-WFBGA,CSPBGA
供应商设备封装: 8-UCSP(4x2)
包装: 带卷 (TR)
Dual, 300mA, Low-Noise Linear Regulator
with Independent Shutdown in UCSP or TDFN
Load-Transient Considerations
The MAX8559 load-transient response graphs (see the
Typical Operating Characteristics ) show two compo-
nents of the output response: a DC shift in the output
voltage due to the different load currents and the tran-
sient response. Typical overshoot for step changes in
the load current from 10μA to 100mA is 15mV. Increase
the output capacitor’s value and decrease its ESR to
attenuate transient spikes.
Dropout Voltage
A regulator’s minimum input-output voltage differential
(or dropout voltage) determines the lowest usable sup-
ply voltage. In battery-powered systems, this determines
the useful end-of-life battery voltage. Because the
MAX8559 uses an internal P-channel MOSFET pass
transistor, its dropout voltage is a function of the drain-
to-source on-resistance (R DS(ON) ) multiplied by the load
current (see the Typical Operating Characteristics ).
Calculating the Maximum Output Power
in UCSP
The maximum output power of the MAX8559 is limited
by the maximum power dissipation of the package. By
calculating the power dissipation of the package as a
function of the input voltage, output voltages, and out-
put currents, the maximum input voltage can be
obtained. The maximum power dissipation should not
exceed the package’s maximum power rating.
P = (V IN(MAX) - V OUTA ) x I OUTA
+ ( VIN(MAX) - V OUTB ) x I OUTB
where:
V IN(MAX) = maximum input voltage
P MAX = maximum power dissipation of the package
(379mW for the UCSP and 1951mW for the TDFN)
V OUTA = output voltage of OUTA
V OUTB = output voltage of OUTB
I OUTA = maximum output current of OUTA
I OUTB = maximum output current of OUTB
P should be less than P MAX . If P is greater than P MAX ,
consider the TDFN.
Layout Guidelines
Due to the low output noise and tight output voltage
accuracy required by most applications, careful PC
board layout is required. An evaluation kit
(MAX8559EVKIT) is available to speed design.
Follow these guidelines for good PC board layout:
? Keep the input and output paths short and wide if
possible, especially at the ground terminals.
? Use thick copper PC boards (2oz vs. 1oz) to
enhance thermal capabilities.
? Place output, input, and bypass capacitors as close
as possible to the IC.
? Ensure traces to BP and the BP capacitor are away
from noisy sources to ensure low output voltage noise.
8
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