参数资料
型号: MAX8594ETG+T
厂商: Maxim Integrated Products
文件页数: 16/22页
文件大小: 0K
描述: IC PMIC W/DC-DC SUP 24-TQFN
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 2,500
应用: 手持/移动设备
电源电压: 3.1 V ~ 5.5 V
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 24-WFQFN 裸露焊盘
供应商设备封装: 24-TQFN-EP(4x4)
包装: 带卷 (TR)
5-Output PMICs with DC-DC Core Supply for
Low-Cost PDAs
Detailed Description
COR1 Step-Down DC-DC Converter
The COR1 regulator is a proprietary hysteretic PWM
control step-down converter that supplies up to 400mA.
The output voltage is set to either 1V or 1.3V by CV for
the MAX8594 and 1.3V or 1.8V for the MAX8594A.
Under moderate to heavy loading, COR1 operates in a
low-noise PWM mode with constant frequency and
modulated pulse width. Switching harmonics generated
by fixed-frequency operation are consistent and easily
filtered. With light loads (<30mA), COR1 operates in an
efficiency-enhanced Idle Mode? during which the con-
verter switches only as needed to service the load.
Linear Regulators
Power for main logic, a SD card slot, and CODEC are
provided by three LDOs:
? MAIN—Provides 3.3V at a guaranteed 500mA with a
typical current limit of 800mA.
? SDIG—Provides 3.3V at a guaranteed 500mA for SD
cards with a typical current limit of 718mA.
? COR2—Provides 1.8V at a guaranteed 50mA for a
CODEC core with a typical current limit of 98mA.
Note that it may not be possible to draw the full rated
function is ideal for applications that require the output
voltage to fall to 0V in shutdown (True Shutdown). If
True Shutdown is not required, the SW switch can be
bypassed by connecting the boost inductor directly to PV
and removing the bypass cap on SW (C7 in Figure 1).
System Sleep
All regulated outputs turn off when V DBI < 1.25V (or V IN
= 3.0V if DBI = IN, Figure 1). The MAX8594/MAX8594A
resume normal operation when V DBI >1.375V (or V IN =
3.3V if DBI = IN, Figure 1).
Reset Output ( RS )
Reset RS asserts when COR1 falls 20% below its set
level (38% for 1.8V setting in the MAX8594A). RS is an
open-drain, active-low output. Connect a pullup resistor
from RS to the logic supply of the gate receiving the
reset signal. RS deasserts a minimum of 10ms after the
COR1 output is in regulation. Upon application of valid
input power, the MAIN output activates first (if ENM =
high) followed by other outputs (if EN_ = high). Power
and output sequencing are shown in Figure 3.
current of MAIN and SDIG at all operating input volt-
V IN
V IN = 3.7V
V IN = 3.33V
ages due to the dropout limitations of those regulators.
The typical dropout resistance of the MAIN regulator is
0.7 ? (350mV drop at 500mA), and the typical dropout
resistance of the SDIG regulator is 0.85 ? (525mV drop
at 500mA).
All voltage outputs have separate enable inputs (ENM,
ENL, ENSD, ENC1, and ENC2); however, no other out-
3.3V MAIN
COR1
V IN = 3.3V
V IN = 3.0V
MAIN AT 90%
MAIN AT 86%
put turns on until MAIN is in regulation. MAIN cannot be
activated until V IN exceeds the DBI threshold. When
SDIG is turned off, reverse current is blocked so the
SDIG output can be biased with an external source
when no power is present at IN. Leakage current is typ-
ically 3μA with 3.3V at SDIG.
RS
LBO
DBO
COR1 AT 90%
20ms RS
DEASSERT
DELAY
LCD DC-DC Boost
The MAX8594/MAX8594A include a low-current, high-
voltage boost DC-DC converter for LCD bias. This circuit
can output up to 28V and is adjustable with either an ana-
log or PWM control signal using external components.
SW provides an input-power disconnect for the LCD
when ENL is low (off). The input-power disconnect
Idle Mode is a trademark of Maxim Integrated Products, Inc.
Figure 3. Power Sequence for Rising and Falling Input Voltage.
Note that V IN thresholds are for LBI and DBI connected to V IN .
Other thresholds can be set with resistors.
16
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