参数资料
型号: MAX8625AETD+T
厂商: Maxim Integrated Products
文件页数: 9/16页
文件大小: 0K
描述: IC REG BUCK BST SYNC 0.8A 14TDFN
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 1
类型: 降压(降压),升压(升压)
输出类型: 两者兼有
输出数: 1
输出电压: 3.3V,1.25 V ~ 4 V
输入电压: 2.5 V ~ 5.5 V
PWM 型: 电流模式
频率 - 开关: 1MHz
电流 - 输出: 800mA
同步整流器:
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 14-WFDFN 裸露焊盘
包装: 标准包装
供应商设备封装: 14-TDFN-EP(3x3)
其它名称: MAX8625AETD+TDKR
High-Efficiency, Seamless Transition,
Step-Up/Down DC-DC Converter
LX1
LX2
IN
P1
N1
N2
P2
OUT
UVLO
P1
CURRENT SENSE
ON
SKIP
REF
REFERENCE
GND
MAX8625A
Figure 1. Simplified Block Diagram
1.25V
125mV
Gm
PWM/PFM
CONTROL
OSCILLATOR
FB
times. This reduces the ripple and removes any mode
transitions from boost-only or buck-only to hybrid modes
as seen in competing H-bridge converters.
The time spent in each phase is set by a PWM con-
troller, using timers and/or peak-current regulation on a
cycle-by-cycle basis. The heart of the PWM control
block is a comparator that compares the output volt-
age-error feedback signal and the sum of the current-
sense and slope compensation signals. The current-
mode control logic regulates the inductor current as a
function of the output error voltage signal. The current-
sense signal is monitored across the MOSFETs (P1, N1,
and N2). A fixed time delay of approximately 30ns
occurs between turning the P1 and N2 MOSFETs off,
and turning the N1 and P2 MOSFETs on. This dead
time prevents efficiency loss by preventing “shoot-
through” current.
Step-Down Operation (V IN > V OUT )
During medium and heavy loads and V IN > V OUT ,
MOSFETs P1 and N2 turn on to begin phase 1 at the
clock edge and ramp up the inductor current. The
duration of phase 1 is set by an internal timer. During
phase 2, N2 turns off, and P2 turns on to further ramp
up inductor current and also transfer charge to the out-
put. This slow charge phase is terminated on a clock
edge and P1 is turned off. The converter now enters the
fast discharge phase (phase 3). In phase 3, N1 turns
on and the inductor current ramps down to the valley
current-regulation point set by the error signal. At the
end of phase 3, both P2 and N1 turn off and another
phase 1 is initiated and the cycle repeats.
With SKIP asserted low, during light loads when induc-
tor current falls to zero in phase 3, the converter switch-
es to phase 4 to reduce power consumption and avoid
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