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参数资料
| 型号： | MAX8634ELA+T |
| 厂商： | Maxim Integrated |
| 文件页数： | 6/13页 |
| 文件大小： | 0K |
| 描述： | IC REG LDO ADJ .3A 8UDFN |
| 产品培训模块： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 标准包装： | 2,500 |
| 稳压器拓扑结构： | 正，可调式 |
| 输出电压： | 可调 |
| 输入电压： | 2.7 V ~ 5.5 V |
| 电压 - 压降（标准）： | 0.09V @ 100mA |
| 稳压器数量： | 2 |
| 电流 - 输出： | 300mA |
| 电流 - 限制（最小）： | 400mA |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 8-WFDFN |
| 供应商设备封装： | 8-uDFN（2x2） |
| 包装： | 带卷 (TR) |
Dual 300mA Pin-Programmable LDO
Linear Regulators
Pin Description
MAX8633
MAX8634
PIN
MAX8635
MAX8636
NAME
FUNCTION
Regulator Input. Supply voltage from 2.7V to 5.5V.
1
1
1
1
IN
Bypass IN with a ceramic capacitor of at least 2.2μF to
GND (see the Capacitor Selection and Regulator
Stability section).
Shutdown Input, Active Low. Drive SHDN logic low to
2
—
—
2
SHDN
shut down both regulators. Connect SHDN to IN or drive
logic high for normal operation (see the Power-On
Sequence (MAX8633/Max8636 Only) section).
LDO1 Shutdown Input, Active Low. Drive SHDN1 logic
—
2
2
—
SHDN1
low to shut down OUT1. Connect SHDN1 to IN or drive
logic high for normal operation.
LDO2 Shutdown Input, Active Low. Drive SHDN2 logic
—
3
5
—
SHDN2
low to shut down OUT2. Connect SHDN2 to IN or drive
logic high for normal operation.
3
4
—
—
—
4
3
4
——
3
4
—
P2
P1
P
Programming Input 2. The state of P1 and P2 selects
one of nine output-voltage options (see Tables 1, 3).
Programming Input 1. The state of P1 and P2 selects
one of nine output-voltage options (see Tables 1, 3).
Programming Input. The state of P selects one of three
output-voltage options for the MAX8634 (see Table 2).
Reset Output, Active Low, Open Drain. RESET goes high
impedance 120ms (min) after V OUT2 rises above 87% of
5
—
—
—
RESET
the nominal output voltage. RESET is forced logic low
when V OUT2 is below 82.5% of the nominal output
voltage. Connect RESET to OUT1, OUT2, or another
voltage of V IN or lower with a pullup resistor.
—
6
5
6
—
6
5
6
BP
GND
Reference Noise Bypass. Bypass BP to GND with a
0.01μF ceramic capacitor to reduce output noise.
Ground
Regulator 2 Output. Guaranteed 300mA output current
(see the Calculating Maximum Output Power section).
7
7
7
7
OUT2
Bypass OUT2 with a ceramic capacitor of at least 2.2μF
to GND (see the Capacitor Selection and Regulator
Stability section).
Regulator 1 Output. Guaranteed 300mA output current
(see the Calculating Maximum Output Power section).
8
8
8
8
OUT1
Bypass OUT1 with a ceramic capacitor of at least 2.2μF
to GND (see the Capacitor Selection and Regulator
Stability section).
Exposed Paddle. Solder the exposed paddle to a large
EP*
EP*
EP*
EP*
EP
pad or circuit-board ground plane to increase thermal
dissipation.
*TDFN package only.
6
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