参数资料
型号: MAX8649AEWE+T
厂商: Maxim Integrated Products
文件页数: 18/31页
文件大小: 0K
描述: IC REG BUCK SYNC ADJ 1.8A 16WLP
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 2,500
类型: 降压(降压)
输出类型: 可调式
输出数: 1
输出电压: 0.75 V ~ 1.38 V
输入电压: 2.5 V ~ 5.5 V
频率 - 开关: 3.25MHz
电流 - 输出: 1.8A
同步整流器:
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 16-UFBGA,WLCSP
包装: 带卷 (TR)
供应商设备封装: 16-WLP(2x2)
1.8A Step-Down Regulator with
Remote Sense in 2mm x 2mm WLP
A
B
C
D
E
OUT
SDA
S
SLAVE ID
ASr
REG PTR
ASr
DATA
A
P
VID0
VID1
V DD
A: I 2 C START COMMAND.
B: I 2 C SLAVE ADDRESS OF SEND OUT.
C: I 2 C REGISTER POINTER SEND OUT.
D: DATA SEND OUT.
E: ISSUE ACKNOWLEDGE AND CHANGES THE OUTPUT VOLTAGE ACCORDING TO NEW I 2 C SETTINGS.
Figure 13. Update Output Operation
Update of Output Operation Mode
If updating the output voltage or Operation Mode regis-
ter for the mode that the ICs are currently operating in,
the output voltage/operation mode is updated at the
4) The master sends an 8-bit register pointer.
5) The slave acknowledges the register pointer.
6) The master sends a data byte.
same time the ICs send the acknowledge for the I 2 C
data byte (see Figure 13).
Slave Address
7)
8)
9)
The slave acknowledges the data byte.
The slave updates with the new data.
The master sends a STOP (P) condition.
A bus master initiates communication with a slave
device (MAX8649/MAX8649A) by issuing a START (S)
condition followed by the slave address (the slave
address byte consists of 7 address bits (1100 000x for
MAX8649; 1100 010x for MAX8649A) and a read/write
bit (R/ W )). After receiving the proper address, the ICs
issues an acknowledge by pulling SDA low during the
ninth clock cycle.
The ICs provide different I 2 C slave addresses, allowing
up to two devices to be used in a system without caus-
ing bus collisions. Contact the factory for availability.
Write Operations
The ICs recognize the write byte protocol as defined in
the SMBus specification and shown in Figures 14a and
14b. The write byte protocol allows the I 2 C master device
to send 1 byte of data to the slave device. The write byte
protocol requires a register pointer address for the sub-
sequent write. The ICs acknowledge any register pointer
In addition to the write-byte protocol, the ICs can write to
multiple registers as shown in Figure 14b. This protocol
allows the I 2 C master device to address the slave only
once and then send data to a sequential block of regis-
ters starting at the specified register pointer.
Use the following procedure to write to a sequential
block of registers:
1) The master sends a start command.
2) The master sends the 7-bit slave address followed
by a write bit.
3) The addressed slave asserts an acknowledge by
pulling SDA low.
4) The master sends the 8-bit register pointer of the
first register to write.
5) The slave acknowledges the register pointer.
6) The master sends a data byte.
even though only a subset of those registers actually
exists in the device. The write byte protocol is as follows:
1) The master sends a start command.
7)
8)
9)
The slave acknowledges the data byte.
The slave updates with the new data.
Steps 6 to 8 are repeated for as many registers in
2) The master sends the 7-bit slave address followed
by a write bit.
3) The addressed slave asserts an acknowledge by
pulling SDA low.
the block, with the register pointer automatically
incremented each time.
10) The master sends a STOP condition.
18
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