参数资料
型号: MAX8649BEWE+T
厂商: Maxim Integrated Products
文件页数: 17/31页
文件大小: 0K
描述: IC REG BUCK SYNC ADJ 1.8A 16WLP
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 2,500
类型: 降压(降压)
输出类型: 可调式
输出数: 1
输出电压: 0.75 V ~ 1.38 V
输入电压: 2.5 V ~ 5.5 V
频率 - 开关: 3.25MHz
电流 - 输出: 1.8A
同步整流器:
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 16-UFBGA,WLCSP
包装: 带卷 (TR)
供应商设备封装: 16-WLP(2x2)
1.8A Step-Down Regulator with
Remote Sense in 2mm x 2mm WLP
SDA
SCL
MASTER
TRANSMITTER/RECEIVER
Figure 11. I 2 CMaster/Slave Configuration
A START condition from the master signals the begin-
ning of a transmission to the ICs. The master termi-
nates transmission by issuing a not acknowledge
SLAVE RECEIVER
SDA OUTPUT
SLAVE
TRANSMITTER/RECEIVER
followed by a STOP condition (see the Acknowledge
section for more information). The STOP condition frees
FROM TRANSMITTER
D7
D6
D0
the bus. To issue a series of commands to the slave,
the master can issue REPEATED START (Sr) com-
mands instead of a STOP command to maintain control
of the bus. In general, a REPEATED START command
is functionally equivalent to a regular START command.
SDA OUTPUT
FROM RECEIVER
SCL FROM
NOT ACKNOWLEDGE
ACKNOWLEDGE
When a STOP condition or incorrect address is detect-
MASTER
1
2
8
9
ed, the MAX8649/MAX8649A internally disconnects
SCL from the serial interface until the next START con-
CLOCK PULSE FOR
dition, minimizing digital noise and feedthrough.
System Configuration
A device on the I 2 C bus that generates a message is
called a transmitter and a device that receives the mes-
START CONDITION
Figure 12. I 2 C Acknowledge
ACKNOWLEDGEMENT
sage is a receiver. The device that controls the mes-
sage is the master and the devices that are controlled
by the master are called slaves. See Figure 11.
Acknowledge
The number of data bytes between the START and
STOP conditions for the transmitter and receiver are
unlimited. Each 8-bit byte is followed by an acknowl-
edge bit. The acknowledge bit is a high-level signal put
on SDA by the transmitter during which time the master
generates an extra acknowledge-related clock pulse. A
slave receiver that is addressed must generate an
acknowledge after each byte it receives. Also, a master
receiver must generate an acknowledge after each
byte it receives that has been clocked out of the slave
transmitter. See Figure 12.
The device that acknowledges must pull down the
DATA line during the acknowledge clock pulse, so that
the DATA line is stable low during the high period of the
acknowledge clock pulse (setup and hold times must
also be met). A master receiver must signal an end of
data to the transmitter by not generating an acknowl-
edge on the last byte that has been clocked out of the
slave. In this case, the transmitter must leave SDA high
to enable the master to generate a STOP (P) condition.
Register Reset
The I 2 C resisters reset back to their default values when
the voltage at either IN1 or V DD drops below the
corresponding UVLO threshold (see the Electrical
Characteristics table).
______________________________________________________________________________________
17
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