参数资料
型号: MAX8688BLETG+T
厂商: Maxim Integrated Products
文件页数: 20/38页
文件大小: 0K
描述: IC PWR SUPPLY CTRLR/MONTR 24TQFN
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 2,500
应用: 电源控制器/监控器
电源电压: 3 V ~ 3.6 V
电流 - 电源: 6.7mA
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 24-WFQFN 裸露焊盘
供应商设备封装: 24-TQFN-EP(4x4)
包装: 带卷 (TR)
Digital Power-Supply Controller/Monitor
with PMBus Interface
A3/ONOFF Operation
In addition to providing address information to the
MAX8688, A3/ONOFF can also be used as a control sig-
nal for turning the POL on or off, similar to the OPERATION
command. To use A3/ONOFF to control the POL, config-
ure the A3 Control Enable bit in MFR_MODE command.
When A3 control is enabled, a transition of A3/ONOFF
from low to high turns the POL on, as if the MAX8688 has
received an OPERATION ON command. A transition of
A3/ONOFF from high to low initiates a soft-off to the POL
—as if the MAX8688 has received an OPERATION OFF
command (soft-off, with sequencing). The MAX8688 still
responds to the PMBus OPERATION command while
A3 control is enabled. To detect the A3/ONOFF input,
the A3/ONOFF signal pulse width has to satisfy the
t A3_LOW and t A3_HIGH requirement to be detected. If
disabled (cleared to 0), the MAX8688 ignores the
A3/ONOFF state and function as directed by the OPER-
ATION command only.
The dual functionality of A3/ONOFF of the MAX8688
requires the system enable signal to be isolated from
A3/ONOFF until the address setting has been read and
latched by the MAX8688. Figure 11 shows one imple-
mentation for the three possible states of the
A3/ONOFF setting. In each case, the system enable
signal (MAX8688_EN) is applied to the input of a three-
state buffer whose output is kept in the high-impedance
state by a control input signal (HIZ_EN) for a time peri-
od during which the MAX8688 reads and latches the
A3/ONOFF address setting. After this period, the con-
trol signal HIZ_EN goes low and allows the system
enable signal to be applied to the MAX8688 A3/ONOFF
pin. After a t A3_LOW , the MAX8688_EN signal transi-
tions from low to high and causes the MAX8688s to
commence POL startup operations.
3.3V
33k ?
MAX8688_EN
MAX8688
A3/ONOFF
A2/SDAE
HIZ_EN
U1
A1/SCLE
REFO
1 μ F
AVDD
MAX8688_UVLO
REFO
MAX8688
A3/ONOFF
A2/SDAE
HIZ_EN
t RST_WAIT
U2
A1/SCLE
REFO
1 μ F
MAX8688_EN
A3/ONOFF
t A3_LOW
MAX8688
A3/ONOFF
U3
33k ?
A2/SDAE
A1/SCLE
REFO
1 μ F
HIZ_EN PLACES U1, U2, AND U3 OUTPUTS IN HIGH-IMPEDANCE STATE WHEN ASSERTED.
U1, U2, AND U3 ARE NOT NECESSARY IF AN EEPROM IS ATTACHED TO A1/SCLE AND A2/SDAE.
A1/SCLE, A2/SDAE ARE EITHER PULLED UP OR PULLED DOWN WITH 33k ? WHEN CONNECTED
TO AN EEPROM.
Figure 11. Application Diagram with A3/ONOFF as Both Address and On/Off Control Signal
20
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