参数资料
型号: MAX8720ETX+T
厂商: Maxim Integrated Products
文件页数: 28/31页
文件大小: 0K
描述: IC CNTRL VID STP DWN 36-TQFN
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 2,500
应用: 控制器,CPU GPU
输入电压: 2 V ~ 28 V
输出数: 1
输出电压: 0.28 V ~ 1.85 V
工作温度: 0°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 36-WFQFN 裸露焊盘
供应商设备封装: 36-TQFN 裸露焊盘(6x6)
包装: 带卷 (TR)
Dynamically Adjustable 6-Bit VID
Step-Down Controller
QSOP LAYOUT EXAMPLE
CC
V CC
QFN LAYOUT EXAMPLE
REF
V DD
ANALOG
GROUND
POWER
GROUND
ANALOG
GROUND
POWER
GROUND
CONNECT AGND
AND PGND TO THE
CONNECT AGND
AND PGND TO THE
CONTROLLER AT
ONE POINT ONLY
CONTROLLER AT
ONE POINT ONLY
AS SHOWN
OUTPUT
AS SHOWN
INPUT
C IN
GROUND
C IN
POWER STAGE LAYOUT EXAMPLE
Figure 12. PC Board Layout Example
PC Board Layout Guidelines
Careful PC board layout is critical to achieving low
switching losses and clean, stable operation. The
switching power stage requires particular attention
(Figure 12). If possible, mount all of the power compo-
nents on the top side of the board, with their ground
terminals flush against one another. Follow these guide-
lines for good PC board layout:
? Keep the high-current paths short, especially at the
ground terminals. This practice is essential for sta-
ble, jitter-free operation.
? Keep the power traces and load connections short.
This practice is essential for high efficiency. Using
thick copper PC boards (2oz vs. 1oz) can enhance
full-load efficiency by 1% or more. Correctly routing
PC board traces is a difficult task that must be
approached in terms of fractions of centimeters,
where a single milliohm of excess trace resistance
causes a measurable efficiency penalty.
? When trade-offs in trace lengths must be made, it is
preferable to allow the inductor charging path to be
made longer than the discharge path. For example,
it is better to allow some extra distance between the
input capacitors and the high-side MOSFET than to
allow distance between the inductor and the low-
side MOSFET or between the inductor and the out-
put filter capacitor.
? Route high-speed switching nodes (BST, LX, DH, and
DL) away from sensitive analog areas (REF, FB).
28
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