参数资料
型号: MAX8744AETJ+
厂商: Maxim Integrated Products
文件页数: 28/36页
文件大小: 0K
描述: IC CNTRLR PWR SUP QUAD 32TQFN
标准包装: 60
应用: 控制器,笔记本电脑电源系统
输入电压: 6 V ~ 26 V
输出数: 4
输出电压: 3.3V,5V,1 V ~ 26 V
工作温度: 0°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 32-WFQFN 裸露焊盘
供应商设备封装: 32-TQFN-EP(5x5)
包装: 管件
High-Efficiency, Quad-Output, Main Power-
Supply Controllers for Notebook Computers
current, allowing accurate current-limit protection.
However, the parasitic inductance of the current-sense
resistor can cause current-limit inaccuracies, especially
when using low-value inductors and current-sense
resistors. This parasitic inductance (L ESL ) can be can-
celed by adding an RC circuit across the sense resistor
with an equivalent time constant:
The actual capacitance value required relates to the
physical size needed to achieve low ESR, as well as to
the chemistry of the capacitor technology. Thus, the
capacitor is usually selected by ESR and voltage rating
rather than by capacitance value (this is true of tanta-
lums, OS-CONs, polymers, and other electrolytics).
When using low-capacity filter capacitors, such as
ceramic capacitors, size is usually determined by the
C EQ R 1 =
L ESL
R SENSE
capacity needed to prevent V SAG and V SOAR from
causing problems during load transients. Generally,
once enough capacitance is added to meet the over-
R CS = ?
R 1 + R 2 ? ?
?
Alternatively,  high-power  applications  that  do  not
require highly accurate current-limit protection may
reduce the overall power dissipation by connecting a
series RC circuit across the inductor (Figure 7B) with
an equivalent time constant:
? R 2 ?
R DCR
and:
shoot requirement, undershoot at the rising load edge
is no longer a problem (see the V SAG and V SOAR equa-
tions in the Transient Response section). However, low-
capacity filter capacitors typically have high ESR zeros
that may affect the overall stability (see the Output-
Capacitor Stability Considerations section).
Output-Capacitor Stability Considerations
Stability is determined by the value of the ESR zero rel-
ative to the switching frequency. The boundary of insta-
bility is given by the following equation:
? R 1 + R 2 ?
f ESR ≤ OSC
R DCR =
L ? 1 1 ?
C EQ ? ?
f
π
where R CS is the required current-sense resistance,
and R DCR is the inductor’s series DC resistance. Use
where:
the typical inductance and R DCR values provided by
the inductor manufacturer.
Output Capacitor Selection
f ESR =
1
2 π R ESR C OUT
V RIPPLE ( P – P ) = IDLE ESR
The output filter capacitor must have low enough equiva-
lent series resistance (ESR) to meet output ripple and
load-transient requirements, yet have high enough ESR to
satisfy stability requirements. The output capacitance
must be high enough to absorb the inductor energy while
transitioning from full-load to no-load conditions without
tripping the overvoltage fault protection. When using high
capacitance, low-ESR capacitors (see stability require-
ments), the filter capacitor’s ESR dominates the output
voltage ripple. So the output capacitor’s size depends on
the maximum ESR required to meet the output voltage
ripple (V RIPPLE(P-P) ) specifications:
V RIPPLE(P-P) = R ESR I LOAD(MAX) LIR
In idle mode, the inductor current becomes discontinu-
ous, with peak currents set by the idle mode current-
sense threshold (V IDLE = 0.2V LIMIT ). In idle mode, the
no-load output ripple may be determined as follows:
V R
R SENSE
For a typical 300kHz application, the ESR zero frequency
must be well below 95kHz, preferably below 50kHz.
Tantalum and OS-CON capacitors in widespread use
at the time of publication have typical ESR zero fre-
quencies of 25kHz. In the design example used for
inductor selection, the ESR needed to support 25mV P-P
ripple is 25mV/1.5A = 16.7m Ω . One 220μF/4V Sanyo
polymer (TPE) capacitor provides 15m Ω (max) ESR.
This results in a zero at 48kHz, well within the bounds
of stability.
For low-input voltage applications where the duty cycle
exceeds 50% (V OUT /V IN ≥ 50%), the output ripple volt-
age should not be greater than twice the internal slope-
compensation voltage:
V RIPPLE ≤ 0.02 x V OUT
where V RIPPLE equals Δ I INDUCTOR x R ESR . The worst-
case ESR limit occurs when V IN = 2 x V OUT , so the above
equation may be simplified to provide the following
boundary condition:
R ESR ≤ 0.04 x L x f SW
28
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