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参数资料
| 型号： | MAX8784ETL+ |
| 厂商： | Maxim Integrated Products |
| 文件页数： | 21/24页 |
| 文件大小： | 0K |
| 描述： | IC REG STP UP W/AMP 40-TQFN |
| 产品培训模块： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 标准包装： | 60 |
| 应用： | LCD 电视机/监控器 |
| 电源电压： | 4 V ~ 5.5 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 40-WFQFN 裸露焊盘 |
| 供应商设备封装： | 40-TQFN-EP（5x5） |
| 包装： | 管件 |
Step-Up Regulator, Internal Charge Pumps, Switch
Control, and Operational Amplifier for TFT LCDs
R 4 = R 3 × FBN GOFF
Pump Capacitors
Increasing the pump capacitor value (C4, C6, and C7)
lowers the effective source impedance and increases
the output-current capability. Increasing the capaci-
tance indefinitely has a negligible effect on output cur-
rent capability because the internal switch resistance
and the diode impedance place a lower limit on the
source impedance. A 0.1μF ceramic capacitor works
well in most low-current applications. For the negative
charge pump, the flying capacitor’s voltage rating must
exceed the following:
V CX > n × V SUP
where n is the stage number in which the flying capaci-
tor appears.
For the positive charge pump, the pump capacitor’s
Adjust the negative charge-pump regulator’s output
voltage by connecting a resistive voltage-divider from
VGOFF to REF with the center tap connected to FBN
(Figure 1). Select R3 in the 20k ? to 68k ? range.
Calculate R4 with the following equation:
V ? V
V REF ? V FBN
where V REF - V FBN is the negative charge-pump regula-
tor’s feedback set point. Note that REF can only source
up to 50μA. Using a resistor less than 20k ? for R2 results
in higher bias current than REF can supply.
PCB Layout Grounding
Careful PCB layout is important for proper operation.
Use the following guidelines for good PCB layout:
voltage rating must exceed the following:
V C 6 > V SUP
V C 7 > 2 x V SUP
Charge-Pump Output Capacitor
Increasing the output capacitance or decreasing the
ESR reduces the output ripple voltage and the peak-to-
peak transient voltage. With ceramic capacitors, the
output-voltage ripple is dominated by the capacitance
value. Use the following equation to approximate the
required capacitor value:
?
Minimize the area of respective high-current loops
by placing step-up regulator’s inductor, diode, and
output capacitors near its input capacitors and its
LX and PGND pins. For the step-up regulator, the
high-current input loop goes from the positive termi-
nal of the input capacitor to the inductor, to the IC’s
LX pins, out of PGND, and to the input capacitor’s
negative terminal. The high-current output loop is
from the positive terminal of the input capacitor to
the inductor, to the output diode (D1), to the posi-
tive terminal of the output capacitors, reconnecting
between the output capacitor and input capacitor
ground terminals. Connect these loop components
C OUT _ CP ≥
I LOAD _ CP
2 f OSC V RIPPLE _ CP
with short, wide connections. Avoid using vias in
the high-current paths. If vias are unavoidable, use
many vias in parallel to reduce resistance and
inductance.
R 6 = R 5 × ? POUT ? 1 ?
where C OUT _ CP is the output capacitor of the charge
pump, I LOAD _ CP is the load current of the charge
pump, and V RIPPLE_CP is the peak-to-peak value of the
output ripple.
Output-Voltage Selection
Adjust the positive charge-pump regulator’s output volt-
age by connecting a resistive voltage-divider from
POUT to GND with the center tap connected to FBP
(Figure 1). Select the lower resistor of divider R5 in the
10k ? to 30k ? range. Calculate upper resistor R6 with
the following equation:
? V ?
? V FBP ?
where V FBP is the positive charge-pump regulator’s
feedback set point.
?
?
Create a power ground island (PGND) for the step-
up regulator, consisting of the input and output
capacitor grounds and the PGND pin. Connect all
these together with short, wide traces or a small
ground plane. Create an analog ground plane
(AGND) consisting of the AGND pin, all the feed-
back-divider ground connections, the COMP,
ADEL, and GDBL capacitor ground connections,
and the device’s exposed backside pad.
Place all feedback voltage-divider resistors as
close as possible to their respective feedback pins.
The divider’s center trace should be kept short.
Placing the resistors far away causes their FB
traces to become antennas that can pick up switch-
ing noise. Care should be taken to avoid running
any feedback trace near LX, DRVN, C1N, C1P,
C2N, or C2P.
______________________________________________________________________________________
21
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| MAX8784ETL+ | 功能描述:显示驱动器和控制器 Reg, CP, Op Amp for TFT LCDs RoHS:否 制造商:Panasonic Electronic Components 工作电源电压:2.7 V to 5.5 V 最大工作温度: 安装风格:SMD/SMT 封装 / 箱体:QFN-44 封装:Reel |
| MAX8784ETL+T | 功能描述:显示驱动器和控制器 Reg, CP, Op Amp for TFT LCDs RoHS:否 制造商:Panasonic Electronic Components 工作电源电压:2.7 V to 5.5 V 最大工作温度: 安装风格:SMD/SMT 封装 / 箱体:QFN-44 封装:Reel |
| MAX8784EVKIT+ | 功能描述:显示开发工具 MAX8784 Eval Kit RoHS:否 制造商:4D Systems 产品:4Display Shields 工具用于评估:?OLED-160-G1, ?OLED-160-G2 接口类型:Serial 工作电源电压:5 V |
| MAX8785AETI+ | 功能描述:显示驱动器和控制器 Full-Bridge CCFL Controller RoHS:否 制造商:Panasonic Electronic Components 工作电源电压:2.7 V to 5.5 V 最大工作温度: 安装风格:SMD/SMT 封装 / 箱体:QFN-44 封装:Reel |
| MAX8785AETI+T | 功能描述:显示驱动器和控制器 Full-Bridge CCFL Controller RoHS:否 制造商:Panasonic Electronic Components 工作电源电压:2.7 V to 5.5 V 最大工作温度: 安装风格:SMD/SMT 封装 / 箱体:QFN-44 封装:Reel |
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