参数资料
型号: MAX8785ETI+
厂商: Maxim Integrated
文件页数: 8/19页
文件大小: 0K
描述: IC CCFL CTRL 28-TQFN
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 60
类型: CCFL 控制器
电流 - 电源: 1.5mA
电源电压: 4.5 V ~ 28 V
工作温度: -40°C ~ 85°C
封装/外壳: 28-WFQFN 裸露焊盘
供应商设备封装: 28-TQFN-EP(5x5)
包装: 管件
Full-Bridge Controller for
Piezoelectric Transformers
Pin Description
PIN
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
NAME
RATE
SHDN
CNTL
LSYNC
FLT
TFLT
HF
LF
PCOMP
COMP
IFB
VFB
LX2
GH2
BST2
V DD2
GL2
PGND
GL1
V DD1
BST1
GH1
LX1
FUNCTION
Duty Ratio Ramp Adjustment Input. Connect a feed-forward network between BATT and RATE to adjust the
slope of the internal ramp that adjusts the H-bridge duty cycle with input voltage.
Shutdown Control Input. The IC shuts down when SHDN is pulled to GND.
Brightness Control Input. The usable brightness control range is from 0 to 2V. V CNTL = 0 represents the
minimum brightness (10% DPWM duty cycle), V CNTL = 2V represents the full brightness (100% DPWM duty
cycle). For details, see the Dimming Control s ection.
DPWM Sync Input. DPWM frequency can be synchronized with an external signal on LSYNC. When SEL is
connected to V CC , the duty cycle of the LSYNC signal determines the brightness. For details, see the
Dimming Control section.
Fault Status Output. FLT is an open-drain output and requires a pullup resistor between V CC and FLT. Under
normal conditions, the FLT output is high impedance. FLT pulls low when a fault condition occurs; FLT is
reset on either power or SHDN cycle.
Fault Time-Out Setting. Connect a capacitor from TFLT to GND to set the time out period. For details, see
the Setting the Fault Delay Time section.
Maximum Switching Frequency Adjustment Input. Connect a resistor from HF to GND to set the maximum
sweeping frequency of the main oscillator.
DPWM Frequency Adjustment Input. Connect a resistor from LF to GND to set the DPWM oscillator
Phase-Lock Loop (PLL) Compensation Pin. Connect a capacitor between PCOMP and GND to compensate
the PLL.
Transconductance Error-Amplifier Output. The COMP voltage controls the voltage-controlled oscillator to
adjust the switching frequency. Connect a capacitor from COMP to GND.
Lamp Current-Feedback Input. IFB regulates the average lamp-current feedback to 800mV (typ) by
controlling the switching frequency. For details, see the Lamp-Current Regulation section.
Secondary Voltage-Feedback Input. A resistive voltage-divider between the high-voltage terminal of the
transformer and GND sets the maximum peak lamp voltage during striking and lamp-out fault. Add 1nF
capacitor from VFB to GND for noise rejection. For details, see the Lamp-Out Detection and Overvoltage
Protection section.
GH2 Gate-Driver Return. LX2 is the input to the primary current-limit comparator. The controller senses the
voltage across the low-side MOSFET (LX2 - PGND) for primary overcurrent condition.
High-Side MOSFET Gate-Driver Output
GH2 Gate-Driver Supply Input. Connect a 0.1μF capacitor from LX2 to BST2.
GL2 Low-Side Gate-Driver Supply Input. Connect V DD2 to V CC . Bypass V DD2 with a 1μF capacitor to PGND.
Low-Side MOSFET Gate-Driver Output
Power Ground. PGND is the return of GL1 and GL2 gate drivers.
Low-Side MOSFET Gate-Driver Output
GL1 Low-Side Gate-Driver Supply Input. Connect V DD1 to V CC . Bypass V DD1 with a 1μF capacitor to PGND.
GH1 Gate-Driver Supply Input. Connect a 0.1μF capacitor from LX1 to BST1.
High-Side MOSFET Gate-Driver Output
GH1 Gate-Driver Return. LX1 is the input to the primary current-limit comparator. The controller senses the
voltage across the low-side MOSFET (LX1 - PGND) for primary overcurrent condition.
8
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