参数资料
型号: MAX8791BGTA+T
厂商: Maxim Integrated
文件页数: 9/12页
文件大小: 0K
描述: IC MOSF DRIVER 1PH SYNCH 8TQFN
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 2,500
配置: 高端和低端,同步
输入类型: 差分
延迟时间: 14ns
电流 - 峰: 2.7A
配置数: 1
输出数: 2
高端电压 - 最大(自引导启动): 36V
电源电压: 4.2 V ~ 5.5 V
工作温度: -40°C ~ 105°C
安装类型: 表面贴装
封装/外壳: 8-WQFN 裸露焊盘
供应商设备封装: 8-TQFN-EP
包装: 带卷 (TR)
Single-Phase, Synchronous MOSFET Drivers
? V
? ? I
?
PD ( N H RESISTIVE ) = ? OUT ? ? LOAD ? R DS ( ON )
PD ( N H SWITCHING ) = ?
?+
?
? ? I GATE ?
? ?
5V Bias Supply (V DD )
V DD provides the supply voltage for the internal logic cir-
cuits. Bypass V DD with a 1μF or larger ceramic capaci-
tor to GND to limit noise to the internal circuitry. Connect
these bypass capacitors as close as possible to the IC.
Input Undervoltage Lockout
When V DD is below the UVLO threshold, DH and DL
are held low. Once V DD is above the UVLO threshold
and while PWM is low, DL is driven high and DH is
driven low. This prevents the output of the converter
from rising before a valid PWM signal is applied.
Low-Power Pulse Skipping
The MAX8791/MAX8791B enter into low-power pulse-
skipping mode when SKIP is pulled low. In skip mode,
an inherent automatic switchover to pulse-frequency
modulation (PFM) takes place at light loads. A zero-
crossing comparator truncates the low-side switch on-
time at the inductor current ’s zero crossing. The
comparator senses the voltage across LX and GND.
Once V LX - V GND drops below the zero-crossing com-
parator threshold (see the Electrical Characteristics),
the comparator forces DL low. This mechanism causes
the threshold between pulse-skipping PFM and non-
skipping PWM operation to coincide with the boundary
between continuous and discontinuous inductor-cur-
rent operation. The PFM/PWM crossover occurs when
the load current of each phase is equal to 1/2 the peak-
to-peak ripple current, which is a function of the induc-
tor value. For a battery input range of 7V to 20V, this
threshold is relatively constant, with only a minor
dependence on the input voltage due to the typically
low duty cycles. The switching waveforms may appear
noisy and asynchronous when light loading activates
the pulse-skipping operation, but this is a normal oper-
ating condition that results in high light-load efficiency.
Applications Information
Power-MOSFET Selection
Most of the following MOSFET guidelines focus on the
challenge of obtaining high load-current capability
when using high-voltage (> 20V) AC adapters. Low-
current applications usually require less attention. The
high-side MOSFET (N H ) must be able to dissipate the
resistive losses plus the switching losses at both
V IN(MIN) and V IN(MAX) . Calculate both these sums.
Ideally, the losses at V IN(MIN) should be roughly equal
to losses at V IN(MAX) , with lower losses in between. If
the losses at V IN(MIN) are significantly higher than the
losses at V IN(MAX) , consider increasing the size of N H
(reducing R DS(ON) but increasing C GATE ). Conversely,
if the losses at V IN(MAX) are significantly higher than the
losses at V IN(MIN) , consider reducing the size of N H
(increasing R DS(ON) but reducing C GATE ). If V IN does
not vary over a wide range, the minimum power dissi-
pation occurs where the resistive losses equal the
switching losses. Choose a low-side MOSFET that has
the lowest possible on-resistance (R DS(ON) ), comes in
a moderate-sized package (i.e., one or two 8-pin SOs,
DPAK, or D2PAK), and is reasonably priced. Ensure
that the DL gate driver can supply sufficient current to
support the gate charge and the current injected into
the parasitic gate-to-drain capacitor caused by the
high-side MOSFET turning on; otherwise, cross-con-
duction problems can occur.
MOSFET Power Dissipation
Worst-case conduction losses occur at the duty factor
extremes. For the high-side MOSFET (N H ), the worst-
case power dissipation due to resistance occurs at the
minimum input voltage:
2
? V IN ? ? η TOTAL ?
where η TOTAL is the total number of phases. Generally,
a small high-side MOSFET is desired to reduce switch-
ing losses at high input voltages. However, the R DS(ON)
required to stay within package-power dissipation often
limits how small the MOSFETs can be. Again, the opti-
mum occurs when the switching losses equal the con-
duction (R DS(ON) ) losses. High-side switching losses
do not usually become an issue until the input is
greater than approximately 15V.
Calculating the power dissipation in high-side
MOSFETs (N H ) due to switching losses is difficult since
it must allow for difficult quantifying factors that influ-
ence the turn-on and turn-off times. These factors
include the internal gate resistance, gate charge,
threshold voltage, source inductance, and PCB layout
characteristics.
The following switching-loss calculation provides only a
very rough estimate and is no substitute for prototype
evaluation, preferably including verification using a
thermocouple mounted on N H :
? V IN ( MAX ) I LOAD f SW ? ? Q G ( SW ) ?
n TOTAL
C OSS V IN 2 f SW
2
where C OSS is the N H MOSFET’s output capacitance,
Q G(SW) is the charge needed to turn on the high-side
MOSFET, and I GATE is the peak gate-drive source/sink
current (5A typ).
_______________________________________________________________________________________
9
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