参数资料
型号: MAX8791GTA+
厂商: Maxim Integrated
文件页数: 8/12页
文件大小: 0K
描述: IC MOSFET DRIVER 8-TQFN
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 100
配置: 高端和低端,同步
输入类型: PWM
延迟时间: 14ns
电流 - 峰: 2.7A
配置数: 1
输出数: 2
高端电压 - 最大(自引导启动): 36V
电源电压: 4.2 V ~ 5.5 V
工作温度: -40°C ~ 105°C
安装类型: 表面贴装
封装/外壳: 8-WQFN 裸露焊盘
供应商设备封装: 8-TQFN-EP
包装: 管件
Single-Phase, Synchronous MOSFET Drivers
V DD
BST
PWM
THERMAL SHUTDOWN
DRIVER LOGIC
AND
DEAD-TIME
DRV
DH
LX
CONTROL
UVLO
DRV#
V DD
SKIP
DL
Figure 4. Overview Block Diagram
LX
ZX DETECTION
PAD
GND
Adaptive Shoot-Through Protection
The DH and DL drivers are optimized for driving mod-
erately sized high-side and larger low-side power
MOSFETs. This is consistent with the low duty factor
seen in the notebook CPU environment, where a large
V IN - V OUT differential exists. Two adaptive dead-time
circuits monitor the DH and DL outputs and prevent the
opposite-side FET from turning on until the other is fully
off. The MAX8791/MAX8791B constantly monitor the
low-side driver output (DL) voltage, and only allow the
high-side driver to turn on when DL drops below the
adaptive threshold. Similarly, the controller monitors the
high-side driver output (DH), and prevents the low side
from turning on until DH falls below the adaptive thresh-
old before allowing DL to turn on.
The adaptive driver dead time allows operation without
shoot-through with a wide range of MOSFETs, minimiz-
ing delays and maintaining efficiency. There must be a
low-resistance, low-inductance path from the DL and
DH drivers to the MOSFET gates for the adaptive dead-
time circuits to work properly; otherwise, the sense cir-
cuitry in the MAX8791/MAX8791B interprets the
MOSFET gates as off while charge actually remains.
Use very short, wide traces (50 mils to 100 mils wide if
the MOSFET is 1in from the driver).
Internal Boost Switch
The MAX8791/MAX8791B use a bootstrap circuit to
generate the necessary drive voltage to fully enhance
the high-side n-channel MOSFET. The internal p-chan-
nel MOSFET creates an ideal diode, providing a low
voltage drop between V DD and BST.
The selected high-side MOSFET determines appropriate
boost capacitance values (C BST in Figure 1), according
to the following equation:
C BST = Q GATE ? V BST
where Q GATE is the total gate charge of the high-side
MOSFET and ? V BST is the voltage variation allowed on
the high-side MOSFET driver. Choose ? V BST = 0.1V to
0.2V when determining C BST . The boost flying capacitor
should be a low equivalent-series resistance (ESR)
ceramic capacitor.
8
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