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参数资料
| 型号： | MAX8798EVKIT+ |
| 厂商： | Maxim Integrated Products |
| 文件页数： | 26/31页 |
| 文件大小： | 0K |
| 描述： | KIT EVAL FOR MAX8798 |
| 产品培训模块： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 标准包装： | 1 |
| 主要目的： | 特殊用途 DC/DC，LCD 电源 |
| 输出及类型： | 4，非隔离 |
| 功率 - 输出： | 3.56W |
| 输出电压： | 8V，3.2V，21V，-13V |
| 电流 - 输出： | 300mA，150mA，20mA，20mA |
| 输入电压： | 1.8 ~ 6 V |
| 稳压器拓扑结构： | 升压 |
| 频率 - 开关： | 1.2MHz |
| 板类型： | 完全填充 |
| 已供物品： | 板，CD |
| 已用 IC / 零件： | MAX8798 |
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Internal-Switch Boost Regulator with
Integrated 3-Channel Scan Driver for TFT LCDs
Data Byte
The data byte follows successful transmission of the
MAX8798’s slave address (Figure 8). For a read opera-
tion, the MAX8798 outputs the 7 bits corresponding to
the current DAC setting followed by a 0 bit. For a write
operation, the bus master must provide the 7-bit data
corresponding to the desired DAC setting followed by a
1 bit. To program the IC’s EEPROM, the master must
make the last bit a zero. In this situation, the other 7 bits
of data are ignored. For programming, GON must
exceed its programming threshold. Otherwise, pro-
gramming does not occur and the MAX8798 does not
acknowledge the programming command.
DAC Values
Table 5 lists the DAC values and the corresponding
I SET , V SET , and V OUT values.
Acknowledge/Polling
The MAX8798, when addressed, generates an acknowl-
edge pulse after the reception of each byte (Figure 9).
The master device must generate an extra clock pulse
that is associated with this acknowledge bit. The device
that acknowledges has to pull down the SDA line during
the acknowledge clock pulse so that the SDA line is sta-
ble LOW during the HIGH period of the acknowledge-
related clock pulse. Of course, setup and hold times
must be taken into account. The master signals an end
of data to the slave by not generating an acknowledge
bit on the last byte that has been clocked out of the
slave. In this case, the slave leaves the data line HIGH to
enable the master to generate the STOP condition.
The MAX8798 does not generate an acknowledge
while an internal programming cycle is in progress.
Once the internally timed write cycle has started and
Table 5. DAC Settings
7-BIT
I SET
DATA BYTE
V SET (V)
V OUT (V)
the EEPROM inputs are disabled, acknowledge polling
can be initiated. This involves sending a START condi-
tion followed by the device address byte. Only if the
internal write cycle has completed does the MAX8798
0000000
0000001
.
.
.
1111110
1111111
I SET(MAX)
I SET(MAX) -
1-LSB
.
.
.
I SET(MIN) +
1-LSB
I SET(MIN)
V SET(MAX)
V SET(MAX) -
1-LSB
.
.
.
V SET(MIN) +
1-LSB
V SET(MIN)
V MIN
V MIN +
1-LSB
.
.
.
V MAX -
1-LSB
V MAX
respond with an acknowledge pulse, allowing the read
or write sequence to continue.
The MAX8798 does not acknowledge a command to
program the EEPROM if V GON is not high enough to
properly program the device. Also, a program com-
mand must be preceded by a write command. The IC
does not acknowledge a program command or pro-
gram the EEPROM unless the DAC data has been
modified since the most recent program command.
DATA OUTPUT
BY MASTER
D7
D6
D0
NOT ACKNOWLEDGE
DATA OUTPUT
BY MAX8798
ACKNOWLEDGE
SCL FROM
MASTER
1
2
8
9
S
CLK1
CLK2
CLK8
CLK9
START
CONDITION
ACKNOWLEDGE
CLOCK PULSE
Figure 9. I 2 C Bus Acknowledge
26
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