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参数资料
| 型号： | MAX8811EEE+ |
| 厂商： | Maxim Integrated |
| 文件页数： | 5/11页 |
| 文件大小： | 0K |
| 描述： | IC DRVR DL PHASE HS 16-QSOP |
| 产品培训模块： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 标准包装： | 100 |
| 配置： | 高端和低端，同步 |
| 输入类型： | 差分 |
| 延迟时间： | 20ns |
| 电流 - 峰： | 6A |
| 配置数： | 4 |
| 输出数： | 4 |
| 电源电压： | 4.5 V ~ 7 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 16-SSOP（0.154"，3.90mm 宽） |
| 供应商设备封装： | 16-QSOP |
| 包装： | 管件 |
High-Speed, Dual-Phase Driver with
Integrated Boost Diodes
Typical Operating Characteristics (continued)
(V VL1 = V VL2 = V EN = V DLY = 6.5V, 3000pF capacitive load, T A = +25°C, unless otherwise noted.)
SWITCHING WAVEFORMS
MAX8811toc09
VPWM
5V/div
VLX
10V/div
VDL
5V/div
VBST_ AND VL_ WAVEFORMS
MAX8811toc10
VL (AC-COUPLED)
500mV/div
VBST (AC-COUPLED)
200mV/div
100ns/div
VDH
5V/div
f SW = 250kHz
1 μ s/div
VLX
10div
Pin Description
PIN
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
NAME
BST1
DH1
LX1
VL1
DL1
PGND1
EN
DLY
PWM1
PWM2
PGND2
DL2
VL2
LX2
DH2
BST2
FUNCTION
Boost Capacitor Connection for Phase 1. Connect a 0.22μF ceramic capacitor between BST1 and LX1.
High-Side Gate-Driver Output for Phase 1. DH1 is pulled low during shutdown and UVLO.
Inductor Connection for Phase 1
Gate-Drive Supply for DL1. Connect VL1 to a 4.5V to 7V supply. VL1 must be connected to VL2
externally. Bypass the VL1/VL2 connection with a 2.2μF or larger ceramic capacitor to the power ground
plane.
Low-Side Gate-Driver Output for Phase 1. DL1 is pulled low during shutdown and UVLO.
Power Ground for DL1. Connect PGND1 and PGND2 to the power ground plane at the IC.
Enable Input. Drive EN high for normal operation, or low for shutdown.
Delay Time Setting Input. Connect a resistor from DLY to PGND1 to set the dead time between DL falling
and DH rising, or connect DLY to VL1 to use the default delay.
PWM Logic Input for Phase 1. DH1 is high when PWM1 is high; DL1 is high when PWM1 is low.
PWM Logic Input for Phase 2. DH2 is high when PWM2 is high; DL2 is high when PWM2 is low.
Power Ground for DL2. Connect PGND1 and PGND2 to the power ground plane at the IC.
Low-Side Gate-Driver Output for Phase 2. DL2 is pulled low during shutdown and UVLO.
Gate-Drive Supply for DL2. Connect VL2 to a 4.5V to 7V supply. VL1 must be connected to VL2
externally. Bypass the VL1/VL2 connection with a 2.2μF or larger ceramic capacitor to the power ground
plane.
Inductor Connection for Phase 2
High-Side Gate-Driver Output for Phase 2. DH2 is pulled low during shutdown and UVLO.
Boost Capacitor Connection for Phase 2. Connect a 0.22μF ceramic capacitor between BST2 and LX2.
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