参数资料
型号: MAX887HESA+T
厂商: Maxim Integrated Products
文件页数: 7/12页
文件大小: 0K
描述: IC REG BUCK SYNC ADJ 0.6A 8SOIC
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 2,500
类型: 降压(降压)
输出类型: 可调式
输出数: 1
输出电压: 1.25 V ~ 10 V
输入电压: 3.5 V ~ 11 V
PWM 型: 电流模式,混合
频率 - 开关: 300kHz
电流 - 输出: 600mA
同步整流器:
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 8-SOIC(0.154",3.90mm 宽)
包装: 带卷 (TR)
供应商设备封装: 8-SOIC
100% Duty Cycle, Low-Noise,
Step-Down, PWM DC-DC Converter
______________________________________________________________Pin Description
PIN
1
2
3
4
5
6
7
8
NAME
SHDN
FB
REF
VL
GND
SYNC
LX
V+
FUNCTION
Shutdown, Active-Low, Logic-Level Input. Connect SHDN to V+ for normal operation.
Feedback Input. Connect FB to a resistor voltage divider between the output and GND.
Reference Bypass Output. Connect a 0.047μF capacitor to GND very close to the MAX887, within 0.2 in. (5mm).
3.3V Internal Logic Regulator Output. Bypass VL to GND with a 2.2μF capacitor very close to the MAX887,
within 0.2 in. (5mm).
Ground
Oscillator Synchronization and PWM Control Input. SYNC is a logic-level input. Tie SYNC to VL for internal
300kHz PWM operation at all loads. The oscillator synchronizes to the negative edge of an external clock
between 10kHz and 400kHz. The MAX887 operates in PWM mode when SYNC is clocked. Tying SYNC to
GND allows a reduced supply-current mode at light loads.
Inductor Connection to the drain of an internal P-channel MOSFET
Supply-Voltage Input. 3.5V min to 11V max. Bypass V+ to GND with a 0.33μF and large-value electrolytic
capacitor in parallel. These capacitors must be as close to the V+ and GND pins as possible. Place the
0.33μF capacitor within 0.2 in. (5mm) of the MAX887.
SHDN
VL
V+
VL
PFM CURRENT COMPARATOR
1 ?
V+
REF
REF
GND
25mV
GND
100mV
ILIM COMPARATOR
LEVEL
SHIFTER
0.1X
LX
SENSE FET
PWM
RAMP
GEN
COMPARATOR
CONTROL &
SYNC
SYNC
CELL
SLOPE COMPENSATION
FROM CONTROL LOGIC
FB
DRIVER LOGIC
SENSE FET
0.1X
PWM
REF
PWM ON
SIGNAL
50mV
1 ?
FB
FB
NEGLIM
COMPARATOR
GND
REF
PFM
COMPARATOR
REF
OVERVOLTAGE
COMPARATOR
0mV in PFM
ADJ. IN PWM
Figure 1. Simplified Functional Block Diagram
_______________________________________________________________________________________
7
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