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| 型号： | MAX8982MEWO+T |
| 厂商： | Maxim Integrated Products |
| 文件页数： | 41/73页 |
| 文件大小： | 0K |
| 描述： | IC PWR MGMT ICERA E400 42WLP |
| 产品培训模块： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 标准包装： | 2,000 |
| 应用： | 电源，ICERA E400，E450 |
| 输入电压： | 4.1 V ~ 5.5 V |
| 输出数： | 10 |
| 输出电压： | 可编程 |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 42-WFBGA，WLCSP |
| 供应商设备封装： | 42-WLP |
| 包装： | 带卷 (TR) |
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MAX8982A/MAX8982P/MAX8982X
Power-Management ICs for
ICERA E400 Platform
REPEATED START (Sr) commands instead of a STOP
command to maintain control of the bus. In general, a
REPEATED START command is functionally equivalent
to a regular START command.
When a STOP condition or incorrect address is detected,
the ICs internally disconnect SCL from the serial inter-
face until the next START condition, minimizing digital
noise and feedthrough.
System Configuration
A device on the I 2 C bus that generates a message is
called a transmitter, and a device that receives the mes-
sage is a receiver. The device that controls the message
is the master, and the devices that are controlled by the
master are called slaves (Figure 14).
The ICs are slave transmitter/receiver devices, and the
B/B chipset is a master transmitter/receiver. The master
initiates data transfer on the bus and generates SCL to
permit data transfer.
Acknowledge
The number of data bytes between the START and STOP
conditions for the transmitter and receiver are unlimited.
Each 8-bit byte is followed by an acknowledge bit. The
acknowledge bit is a high-level signal put on SDA by the
transmitter during which time the master generates an
extra acknowledge-related clock pulse. A slave receiver
that is addressed must generate an acknowledge after
each byte it receives. Also, a master receiver must
generate an acknowledge after each byte it receives
that has been clocked out of the slave transmitter. See
Figure 15.
The device that acknowledges must pull down the DATA
line during the acknowledge clock pulse, so that the
DATA line is stable low during the high period of the
acknowledge clock pulse (setup and hold times must
also be met). A master receiver must signal an end of
data to the transmitter by not generating an acknowl-
edge on the last byte that has been clocked out of the
slave. In this case, the transmitter must leave SDA high
to enable the master to generate a STOP condition.
SDA
SCL
MASTER
TRANSMITTER/RECEIVER
Figure 14. Master/Slave Configuration
SDA OUTPUT
SLAVE RECEIVER
SLAVE
TRANSMITTER/RECEIVER
FROM TRANSMITTER
D7
D6
D0
NOT ACKNOWLEDGE
SDA OUTPUT
FROM RECEIVER
SCL FROM
ACKNOWLEDGE
MASTER
1
2
8
9
CLOCK PULSE FOR
Figure 15. I 2 C Acknowledge
Maxim Integrated
START CONDITION
ACKNOWLEDGEMENT
41
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相关代理商/技术参数 |
参数描述 |
|---|---|
| MAX8982PEWO+T | 功能描述:PMIC 解决方案 PMIC for ICERA E400/E450 Platform RoHS:否 制造商:Texas Instruments 安装风格:SMD/SMT 封装 / 箱体:QFN-24 封装:Reel |
| MAX8982XEWO+T | 制造商:Maxim Integrated Products 功能描述:POWER MANAGEMENT IC FOR ICERA E400/E450 PLATFORM-MINI CARD - Tape and Reel |
| MAX8986EVKIT+ | 制造商:Maxim Integrated Products 功能描述:PMIC FOR BROADCOM BB ATHENA - Boxed Product (Development Kits) |
| MAX8986EWG+ | 制造商:Maxim Integrated Products 功能描述:POWER MANAGEMENT IC FOR CELL PHONE |
| MAX8986EWG+T | 制造商:Maxim Integrated Products 功能描述:POWER MANAGEMENT IC FOR CELL PHONE,800M 制造商:Maxim Integrated Products 功能描述:PMIC FOR BROADCOM BB ATHENA - Tape and Reel |
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