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参数资料
| 型号： | MAX9013EUA+T |
| 厂商： | Maxim Integrated Products |
| 文件页数： | 8/12页 |
| 文件大小： | 0K |
| 描述： | IC COMPARATOR TTL 8-UMAX |
| 产品培训模块： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 标准包装： | 2,500 |
| 类型： | 带锁销 |
| 元件数： | 1 |
| 输出类型： | 补充型，TTL |
| 电压 - 电源，单路/双路(±)： | 4.5 V ~ 5.5 V |
| 电压 - 输入偏移（最小值）： | 3mV @ 5.5V |
| 电流 - 输入偏压（最小值）： | 0.5µA @ 5V |
| 电流 - 输出（标准）： | 40mA |
| 电流 - 静态（最大值）： | 2.3mA |
| CMRR, PSRR（标准）： | 95dB CMRR，82dB PSRR |
| 传输延迟（最大）： | 9ns |
| 工作温度： | -40°C ~ 85°C |
| 封装/外壳： | 8-TSSOP，8-MSOP（0.118"，3.00mm 宽） |
| 安装类型： | 表面贴装 |
| 包装： | 带卷 (TR) |
MAX9010–MAX9013
SC70, 5ns, Low-Power, Single-Supply,
Precision TTL Comparators
_______________________________________________________________________________________
5
Note 4: Although Common-Mode Input Voltage Range is restricted to -0.2V
≤ VCM ≤ (VCC - 1.9V), either or both inputs can go to either
absolute maximum voltage limit, i.e., from -0.3V to (VCC + 0.3V), without damage. The comparator will make a correct (and fast)
logic decision provided that at least one of the two inputs is within the specified common-mode range. If both inputs are outside
the common-mode range, the comparator output state is indeterminate.
Note 5: For the MAX9012, Input Offset Voltage is defined as the input voltage(s) required to make the OUT output voltage(s) remain
stable at 1.4V. For the MAX9013, it is defined as the average of two input offset voltages, measured by forcing first the OUT
output, then the OUT output to 1.4V.
Note 6: Propagation delay for these high-speed comparators is guaranteed by design because it cannot be accurately measured
with low levels of input overdrive voltage using automatic test equipment in production. Note that for low overdrive
conditions, VOS is added to the overdrive.
Note 7: Differential Propagation Delay, measured either on a single output of the MAX9012/MAX9013 (or between OUT and OUT
outputs on the MAX9013) is defined as:
tPD(±) = |(tPD+) - (tPD-)|.
Note 8: Latch times are guaranteed by design. Latch setup time (tSU) is the interval in which the input signal must be stable prior to
asserting the latch signal. The hold time (tH) is the interval after the latch is asserted in which the input signal must remain
stable. Latch propagation delay (tLPD) is the delay time for the output to respond when the latch enable pin is deasserted
(see Figure 1).
t = 5ns/div
RESPONSE TO -5mV OVERDRIVE
IN: 50mV/div
OUT: 1V/div
0
IN
3V
+100mV
MAX9010–13 toc02
OUT
0
6.0
3.5
1
10
100
4.0
MAX9010
–
13
toc03
OVERDRIVE (mV)
PROPAGATION
DELAY
(ns)
4.5
5.0
5.5
PROPAGATION DELAY
vs. INPUT OVERDRIVE
3.0
tPD(+)
tPD(-)
t = 5ns/div
RESPONSE TO +5mV OVERDRIVE
IN: 50mV/div
OUT: 1V/div
0
IN
3V
-100mV
MAX9010–13 toc01
OUT
0
Typical Operating Characteristics
(VCC = 5V, CL = 15pF, TA = +25°C, unless otherwise noted.)
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