参数资料
型号: MAX9024AUD+T
厂商: Maxim Integrated Products
文件页数: 6/8页
文件大小: 0K
描述: IC COMPARATOR QUAD 14-TSSOP
其它有关文件: Automotive Product Guide
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 2,500
类型: 通用
元件数: 4
输出类型: CMOS,满摆幅,TTL
电压 - 电源,单路/双路(±): 2.5 V ~ 5.5 V,±1.25 V ~ 2.75 V
电压 - 输入偏移(最小值): 1mV @ 5V
电流 - 输入偏压(最小值): 0.003µA @ 5V
电流 - 静态(最大值): 5µA
CMRR, PSRR(标准): 100dB CMRR,80dB PSRR
传输延迟(最大): 8µs
磁滞: 4mV
工作温度: -40°C ~ 125°C
封装/外壳: 14-TSSOP(0.173",4.40mm 宽)
安装类型: 表面贴装
包装: 带卷 (TR)
MAX9021/MAX9022/MAX9024
Micropower, Ultra-Small, Single/Dual/Quad,
Single-Supply Comparators
6
_______________________________________________________________________________________
2) The hysteresis band will be:
VHYS = VTH - VTL = VDD(R2 / (R1 + R2))
3) In this example, let VDD = 5V and VREF = 2.5V.
VTH = 2.5V + 2.5V(R2 / (R1 + R2))
and
VTL = 2.5V[(1 - (R2 / (R1 + R2))]
4) Select R2. In this example, we will choose 1k
.
5) Select VHYS. In this example, we will choose 50mV.
6) Solve for R1.
VHYS = VDD(R2 / (R1 + R2))
0.050V = 5(1000
/(R1 + 1000)) V
where R1
≈ 100k, VTH = 2.525V, and VTL = 2.475V.
The above-described design procedure assumes rail-
to-rail output swing. If the output is significantly loaded,
the results should be corrected.
Board Layout and Bypassing
Use 100nF bypass as a starting point. Minimize signal
trace lengths to reduce stray capacitance. Minimize the
capacitive coupling between IN- and OUT. For slow-
moving input signals (rise time > 1ms), use a 1nF
capacitor between IN+ and IN-.
Biasing for Data Recovery
Digital data is often embedded into a bandwidth and
amplitude-limited analog path. Recovering the data can
be difficult. Figure 2 compares the input signal to a
time-averaged version of itself. This self-biases the
threshold to the average input voltage for optimal noise
margin. Even severe phase distortion is eliminated from
the digital output signal. Be sure to choose R1 and C1
so that:
fCAR >> 1 / (2
πR1C1)
where fCAR is the fundamental carrier frequency of the
digital data stream.
MAX9021
OUT
IN+
IN-
R2
R1
VIN
VREF
VDD
VSS
VDD
Figure 1. Additional Hysteresis
MAX9021
OUT
IN+
IN-
10k
0.1
F
VDD
VIN
VSS
VDD
Figure 2. Time Averaging of the Input Signal for Data Recovery
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