参数资料
型号: MAX902ESD+
厂商: Maxim Integrated Products
文件页数: 2/13页
文件大小: 0K
描述: IC COMPARATOR VOLT 14-SOIC
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 50
类型: 带锁销
元件数: 2
输出类型: TTL
电压 - 电源,单路/双路(±): 5 V ~ 10 V,±2.5 V ~ 5 V
电压 - 输入偏移(最小值): 4mV @ ±5V
电流 - 输入偏压(最小值): 10µA @ ±5V
电流 - 静态(最大值): 8mA,6mA,3mA
CMRR, PSRR(标准): 82.5dB CMRR,80dB PSRR
工作温度: -40°C ~ 85°C
封装/外壳: 14-SOIC(0.154",3.90mm 宽)
安装类型: 表面贴装
包装: 管件
产品目录页面: 1385 (CN2011-ZH PDF)
MAX900–MAX903
High-Speed, Low-Power Voltage Comparators
_______________________________________________________________________________________
9
Definitions of Terms
VOS
Input Offset Voltage: Voltage applied
between the two input terminals to obtain
TTL-logic threshold (+1.4V) at the
output.
tpd+ (D)
Latch Disable-to-Output High Delay:
The propagation delay measured from
the latch-signal crossing the TTL
threshold in a low-to-high transition to
the point of the output crossing TTL
threshold in a low-to-high transition.
VIN
Input Voltage Pulse Amplitude: Usually
set to 100mV for comparator
specifications.
tpd- (D)
Latch Disable-to-Output Low Delay:
The propagation delay measured from
the latch-signal crossing the TTL
threshold in a low-to-high transition to
the point of the output crossing TTL
threshold in a high-to-low transition.
VOD
Input Voltage Overdrive: Usually set to
5mV and in opposite polarity to VIN for
comparator specifications.
ts
Minimum Setup Time: The minimum
time before the negative transition of the
latch signal that an input signal change
must be present in order to be acquired
and held at the outputs.
tpd+
Input-to-Output High Delay: The
propagation delay measured from the
time the input signal crosses the input
offset voltage to the TTL-logic threshold
of an output low-to-high transition
th
Minimum Hold Time: The minimum time
after the negative transition of the latch
signal that an input signal must remain
unchanged in order to be acquired and
held at the output.
tpd-
Input-to-Output Low Delay: The
propagation delay measured from the
time the input signal crosses the input
offset voltage to the TTL-logic threshold
of an output high-to-low transition.
tpw (D)
Minimum Latch-Disable Pulse Width:
The minimum time that the latch signal
must remain high in order to acquire and
hold an input-signal change.
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