参数资料
型号: MAX9246GUM/V+
厂商: Maxim Integrated Products
文件页数: 19/23页
文件大小: 0K
描述: IC DESERIALIZER 21BIT 48TSSOP
标准包装: 39
系列: *
MAX9242/MAX9244/MAX9246/MAX9254
21-Bit Deserializers with Programmable
Spread Spectrum and DC Balance
_______________________________________________________________________________________
5
Note 1: Current into a pin is defined as positive. Current out of a pin is defined as negative. All voltages are referenced to ground,
except VTH and VTL.
Note 2: Maximum and minimum limits over temperature are guaranteed by design and characterization. Devices are production
tested at TA = +25°C.
Note 3: To provide a mid level, leave the input open, or, if driven, put driver in high impedance. High-impedance leakage current
must be less than ±10A.
Note 4: RxCLKOUT limits are scaled based on RxOUT_ measurements, design, and characterization data.
Note 5: One output shorted at a time. Current out of the pin.
Note 6: VTH, VTL, and AC parameters are guaranteed by design and characterization, and are not production tested. Limits are set
at ±6 sigma.
Note 7: CL includes probe and test jig capacitance.
Note 8: RCIP is the period of RxCLKIN_. RCOP is the period of RxCLKOUT.
Note 9: RSKM is measured with less than 150ps cycle-to-cycle jitter on RxCLKIN_.
AC ELECTRICAL CHARACTERISTICS (continued)
(VCC = LVDSVCC = PLLVCC = +3.0V to +3.6V, VCCO = +3.0V to +3.6V, CL = 8pF, PWRDWN = high; SSG = high, open, or low;
DCB = high or low, differential input voltage |VID| = 0.1V to 1.2V, input common-mode voltage VCM = |VID / 2| to 2.4V - |VID / 2|, unless
otherwise noted. Typical values are at VCC = VCCO = LVDSVCC = PLLVCC = +3.3V, |VID| = 0.2V, VCM = +1.25V, TA = +25°C.) (Notes 6, 7, 8)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
RxCLKOUT High Time
RCOH
Figures 5a, 5b
0.35 x
RCOP
ns
RxCLKOUT Low Time
RCOL
Figures 5a, 5b
0.35 x
RCOP
ns
RxOUT_ Setup to RxCLKOUT
RSRC
Figures 5a, 5b
0.3 x
RCOP
ns
RxOUT_ Hold from RxCLKOUT
RHRC
Figures 5a, 5b
0.45 x
RCOP
ns
RxCLKIN_ to RxCLKOUT Delay
RCCD
SSG = low, Figures 6a, 6b
4.5 +
(RCIP / 2)
6.5 +
(RCIP / 2)
8.2 +
(RCIP / 2)
ns
Deserializer Phase-Locked-
Loop Set
RPLLS
Figure 7
65,600 x
RCIP
ns
Deserializer Power-Down Delay
RPDD
Figure 8
100
ns
Deserializer Phase-Locked-
Loop Set from SSG Change
RPLLS2
Figure 9
32,800 x
RCIP
ns
Maximum output
frequency
fRxCLKIN_
+ 3.6%
fRxCLKIN_
+ 4.0%
fRxCLKIN_
+ 4.4%
SSG = high,
Figure 10
Minimum output
frequency
fRxCLKIN_
- 4.4%
fRxCLKIN_
- 4.0%
fRxCLKIN_
- 3.6%
Maximum output
frequency
fRxCLKIN_
+ 1.8%
fRxCLKIN_
+ 2.0%
fRxCLKIN_
+ 2.2%
SSG = open,
Figure 10
Minimum output
frequency
fRxCLKIN_
- 2.2%
fRxCLKIN_
- 2.0%
fRxCLKIN_
- 1.8%
Spread-Spectrum Output
Frequency
fRxCLKOUT
SSG = low
fRxCLKIN_
MHz
Spread-Spectrum Modulation
Frequency
fSSM
Figure 10
fRxCLKIN_ /
1016
Hz
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