参数资料
型号: MAX9247ECM+T
厂商: Maxim Integrated Products
文件页数: 6/17页
文件大小: 0K
描述: IC SERIALIZER LVDS 48-LQFP
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 2,000
功能: 串行器
数据速率: 840Mbps
输入类型: 串行
输出类型: LVDS
输入数: 18
输出数: 1
电源电压: 3 V ~ 3.6 V
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 48-LQFP
供应商设备封装: 48-LQFP(7x7)
包装: 带卷 (TR)
MAX9247
27-Bit, 2.5MHz-to-42MHz
DC-Balanced LVDS Serializer
14
______________________________________________________________________________________
Termination
The MAX9247 has an integrated 100
output-termina-
tion resistor. This resistor damps reflections from
induced noise and mismatches between the transmis-
sion line impedance and termination resistors at the
deserializer input. With PWRDWN = low or with the sup-
ply off, the output termination is switched out and the
LVDS output is high impedance.
Common-Mode Filter
The integrated 100
output termination is made up of
two 50
resistors in series. The junction of the resistors
is connected to the CMF pin for connecting an optional
common-mode filter capacitor. Connect the filter
capacitor to ground close to the MAX9247 as shown in
Figure 15. The capacitor shunts common-mode switch-
ing current to ground to reduce EMI.
LVDS Output Preemphasis (PRE)
The MAX9247 features a preemphasis mode where extra
current is added to the output and causes the ampli-
tude to increase by 40% to 50% at the transition point.
Preemphasis helps to get a faster transition, better eye
diagram, and improve signal integrity. See the
Typical
Operating Characteristics. The additional current is
turned on for a short time (360ps, typ) during data transi-
tion, and then turned off. Enable preemphasis by driving
PRE high.
Power-Down and Power-Off
Driving PWRDWN low stops the PLL, switches out the
integrated 100
output termination, and puts the output
in high impedance to ground and differential. With PWRD-
WN
≤ 0.3V and all LVTTL/LVCMOS inputs ≤ 0.3V or ≥
VCCIN - 0.3V, supply current is reduced to 50A or less.
Driving PWRDWN high starts PLL lock to PCLK_IN and
switches in the 100
output termination resistor. The
LVDS output is not driven until the PLL locks. The LVDS
output is high impedance to ground and 100
differen-
tial. The 100
integrated termination pulls OUT+ and
OUT- together while the PLL is locking so that VOD = 0V.
If VCC = 0, the output resistor is switched out and the LVDS
outputs are high impedance to ground and differential.
PLL Lock Time
The PLL lock time is set by an internal counter. The lock
time is 17,100 PCLK_IN cycles. Power and clock should
be stable to meet the lock-time specification.
Input Buffer Supply
The single-ended inputs (RGB_IN[17:0], CNTL_IN[8:0],
DE_IN, RNG0, RNG1, PRE, PCLK_IN, and PWRDWN)
are powered from VCCIN. VCCIN can be connected to a
1.71V to 3.6V supply, allowing logic inputs with a nomi-
nal swing of VCCIN. If no power is applied to VCCIN
when power is applied to VCC, the inputs are disabled
and PWRDWN is internally driven low, putting the
device in the power-down state.
Power-Supply Sequencing of MAX9247
and MAX9248/MAX9250 Video Link
The MAX9247 and MAX9248/MAX9250 video link can
be powered up in several ways. The best approach is
to keep both MAX9247 and MAX9248 powered down
while supplies are ramping up and PCLK_IN of the
MAX9247 and REFCLK of the MAX9248/MAX9250 are
stabilizing. After all of the power supplies of the
MAX9247 and MAX9248/MAX9250 are stable, including
PCLK_IN and REFCLK, do the following:
1) Power up the MAX9247 first
AC-COUPLING CAPACITOR VALUE
vs. PARALLEL CLOCK FREQUENCY
PARALLEL CLOCK FREQUENCY (MHz)
CAPACITOR
VALUE
(nF)
21
24
27
33
36
39
30
120
80
60
40
20
100
140
0
18
42
FOUR CAPACITORS PER LINK
TWO CAPACITORS PER LINK
Figure 14. AC-Coupling Capacitor Values vs. Clock Frequency
of 18MHz to 42MHz
OUT+
RO/2
CMF
OUT-
CCMF
Figure 15. Common-Mode Filter Capacitor Connection
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