参数资料
型号: MAX9258AEVKIT#
厂商: Maxim Integrated Products
文件页数: 5/53页
文件大小: 0K
描述: EVAL KIT MAX9257A, MAX9258A
标准包装: 1
系列: *
Maxim Integrated Products 13
MAX9257A/MAX9258A
Fully Programmable Serializer/Deserializer
with UART/I2C Control Channel
MAX9257A Pin Description (continued)
MAX9258A Pin Description
PIN
NAME
FUNCTION
TQFN
LQFP
29
34
REM
Remote Power-Up/Power-Down Select Input. Connect REM to ground for power-up to follow
VCC. Connect REM high to VCC through 10kI resistor for remote power-up. REM is internally
pulled down to GND.
30, 31, 32,
35–39
35, 38, 39,
42–46
DIN[0:7]
Data Inputs. DIN[0:7] are internally pulled down to ground.
40
47
DIN8/GPIO0
Data Input/General Purpose Input/Output. When a serial-data word is less than 18 bits word
length, DIN_ not programmed as data input becomes GPIO (Table 22). DIN8 is internally
pulled down to ground.
1, 12, 13
24, 25, 36,
37, 48
N.C.
No Connection. Not internally connected.
EP
Exposed Pad for TQFN Package Only. Connect EP to ground.
PIN
NAME
FUNCTION
1, 12, 13, 24,
25, 36, 37
N.C.
No Connection. Not internally connected.
2
VCC
Digital Supply Voltage. Bypass VCC to GND with 0.1FF and 0.001FF capacitors in parallel as close
as possible to the device with the smallest value capacitor closest to VCC.
3, 14
GND
Digital Supply Ground
4
PD
LVCMOS/LVTTL Power-Down Input. Drive PD high to power up the device and enable all outputs.
Drive PD low to put all outputs in high impedance and reduce supply current. PD is internally
pulled down to ground.
5
VCCLVDS
LVDS Supply Voltage. Bypass VCCLVDS to GNDLVDS with 0.1FF and 0.001FF capacitors in parallel
as close as possible to the device with the smallest value capacitor closest to VCCLVDS.
6
SDI-
Serial LVDS Inverting Input
7
SDI+
Serial LVDS Noninverting Input
8
GNDLVDS
LVDS Supply Ground
9
GNDPLL
PLL Supply Ground
10
VCCPLL
PLL Supply Voltage. Bypass VCCPLL to GNDPLL with 0.1FF and 0.001FF capacitors in parallel as
close to the device as possible with the smallest value capacitor closest to VCCPLL.
11
ERROR
Active-Low, Open-Drain Error Output. ERROR asserts low to indicate a data transfer error was
detected (parity, PRBS, or UART control channel error). ERROR is high to indicate no error detect-
ed. ERROR resets when the error registers are read for parity, control channel errors, and when
PRBS enable bit is reset for PRBS errors. Pull up to VCCOUT with a 1kI resistor.
15
RX
LVCMOS/LVTTL Control Channel UART Output
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