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参数资料
| 型号： | MAX9259GCB/V+T |
| 厂商： | Maxim Integrated Products |
| 文件页数： | 21/51页 |
| 文件大小： | 0K |
| 描述： | IC SERIALIZER GMSL 64TQFP |
| 标准包装： | 750 |
| 系列： | * |
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Gigabit Multimedia Serial Link with Spread
Spectrum and Full-Duplex Control Channel
MAX9259/MAX9260
28 _____________________________________________________________________________________
Parallel Data-Rate Selection
The MAX9259/MAX9260 use the DRS inputs to set the
parallel data rate. Set DRS high to use a low-speed par-
allel data rate in the range of 6.25MHz to 12.5MHz (32-bit
mode) or 8.33MHz to 16.66MHz (24-bit mode). Set DRS
low for normal operation with parallel data rates higher
than 12.5MHz (32-bit mode) or 16.66MHz (24-bit mode).
Audio Channel
The I2S audio channel supports audio sampling rates
from 8kHz to 192kHz and audio word lengths from 4 bits
to 32 bits. The audio bit clock (SCK) does not need to be
synchronized with PCLKIN. The MAX9259 automatically
encodes audio data into a single bit stream synchronous
with PCLKIN. The MAX9260 decodes the audio stream
and stores audio words in a FIFO. Audio rate detection
uses an internal oscillator to continuously determine the
audio data rate and output the audio in I2S format. The
audio channel is enabled by default. When the audio
channel is disabled, the SD pins on both sides are
treated as a regular parallel data pin.
PCLK_ frequencies can limit the maximum supported
audio sampling rate. Table 4 lists the maximum audio
sampling rate for various PCLK_ frequencies. Spread-
spectrum settings do not affect the I2S data rate or WS
clock frequency.
Additional MCLK Output
for Audio Applications
Some audio DACs such as the MAX9850 do not require
a synchronous main clock (MCLK), while other DACs
require MCLK to be a specific multiple of WS. If an audio
DAC chip needs the MCLK to be a multiple of WS, syn-
chronize the I2S audio data with PCLK_ of the GMSL,
which is typical for most applications. Select the PCLK_
to be the multiple of WS, or use a clock synthesis chip,
such as the MAX9491, to regenerate the required MCLK
from PCLK_ or SCK.
For audio applications that cannot directly use the
PCLKOUT output, the MAX9260 provides a divided
MCLK output on DOUT28 at the expense of one less
parallel line in 32-bit mode (24-bit mode is not affected).
By default, DOUT28 operates as a parallel data output
and MCLK is turned off. Set MCLKDIV (MAX9260 regis-
ter 0x12, D[6:0]) to a non-zero value to enable the MCLK
output. Set MCLKDIV to 0x00 to disable MCLK and set
DOUT28 as a parallel data output.
The output MCLK frequency is:
SRC
MCLK
f
MCLKDIV
=
where fSRC is the MCLK source frequency (Table 5) and
MCLKDIV is the divider ratio from 1 to 127.
Table 4. Maximum Audio Sampling Rates for Various PCLK_ Frequencies
WORD LENGTH
(Bits)
PCLK_ FREQUENCY
(DRS = LOW)
(MHz)
PCLK_ FREQUENCY
(DRS = HIGH)
(MHz)
12.5
15
16.6
> 20
6.25
7.5
8.33
> 10
8
> 192
16
> 192
18
185.5
> 192
185.5
> 192
20
174.6
> 192
174.6
> 192
24
152.2
182.7
> 192
152.2
182.7
> 192
32
123.7
148.4
164.3
> 192
123.7
148.4
164.3
> 192
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相关代理商/技术参数 |
参数描述 |
|---|---|
| MAX9259GTN/V+ | 制造商:Maxim Integrated Products 功能描述:GIGABIT MULTIMEDIA SERIAL LINK WITH SPREAD SPECTRUM AND FULL - Rail/Tube |
| MAX9259GTN/V+GG6 | 制造商:Maxim Integrated Products 功能描述:IC SERIALIZER GMSL |
| MAX9259GTN/V+T | 制造商:Maxim Integrated Products 功能描述: |
| MAX9259GTN/V+TGG6 | 制造商:Maxim Integrated Products 功能描述:IC SERIALIZER GMSL |
| MAX9260EVKIT+ | 功能描述:界面开发工具 MAX9260 Eval Kit RoHS:否 制造商:Bourns 产品:Evaluation Boards 类型:RS-485 工具用于评估:ADM3485E 接口类型:RS-485 工作电源电压:3.3 V |
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