- 您现在的位置：买卖IC网 > PDF目录8744 > MAX9311ECJ+ (Maxim Integrated Products)IC CLK/DATA BUFF MUX 2:10 32LQFP PDF资料下载
参数资料
| 型号： | MAX9311ECJ+ |
| 厂商： | Maxim Integrated Products |
| 文件页数： | 10/12页 |
| 文件大小： | 0K |
| 描述： | IC CLK/DATA BUFF MUX 2:10 32LQFP |
| 产品培训模块： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 标准包装： | 250 |
| 类型： | 扇出缓冲器（分配），多路复用器，数据 |
| 电路数： | 1 |
| 比率 - 输入:输出： | 2:10 |
| 差分 - 输入:输出： | 是/是 |
| 输入： | HSTL，LVECL，LVPECL |
| 输出： | LVECL，LVPECL |
| 频率 - 最大： | 3GHz |
| 电源电压： | 2.25 V ~ 3.8 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 32-LQFP |
| 供应商设备封装： | 32-LQFP（7x7） |
| 包装： | 托盘 |
MAX9311/MAX9313
1:10 Differential LVPECL/LVECL/HSTL
Clock and Data Drivers
_______________________________________________________________________________________
7
Detailed Description
The MAX9311/MAX9313 are low skew, 1-to-10 differen-
tial drivers designed for clock and data distribution.
A 2:1 mux selects between the two differential inputs,
CLK0, CLK0 and CLK1, CLK1. The 2:1 mux is switched
by the single-ended CLKSEL input. A logic low selects
the CLK0, CLK0 input. A logic high selects the CLK1,
CLK1 input. The logic threshold for CLKSEL is set by an
internal VBB voltage reference. The CLKSEL input can
be driven to VCC and VEE or by a single-ended LVPECL/
LVECL signal. The selected input is reproduced at 10
differential outputs.
For interfacing to differential HSTL and LVPECL signals,
these devices operate over a +2.25V to +3.8V supply
range, allowing high-performance clock or data distribu-
tion in systems with a nominal +2.5V or +3.3V supply.
For differential LVECL operation, these devices operate
from a -2.25V to -3.8V supply.
The differential inputs can be configured to accept sin-
gle-ended inputs when operating at approximately VCC -
VEE = +3.0V to +3.8V for the MAX9311 or VCC - VEE =
+2.7V to +3.8V for the MAX9313. This is accomplished
by connecting the on-chip reference voltage, VBB, to an
input as a reference. For example, the differential CLK0,
CLK0 input is converted to a noninverting, single-ended
input by connecting VBB to CLK0 and connecting the
single-ended input to CLK0. Similarly, an inverting input
is obtained by connecting VBB to CLK0 and connecting
the single-ended input to CLK0. With a differential input
configured as single-ended (using VBB), the single-
ended input can be driven to VCC and VEE or with a sin-
gle-ended LVPECL/LVECL signal.
When a differential input is configured as a single-ended
input (using VBB), the approximate supply range is VCC -
VEE = +3.0V to +3.8V for the MAX9311 and VCC - VEE =
+2.7V to +3.8V for the MAX9313. This is because one of
the inputs must be VEE + 1.2V or higher for proper oper-
ation of the input stage. VBB must be at least VEE + 1.2V
because it becomes the high-level input when the other
(single-ended) input swings below it. Therefore, mini-
mum VBB = VEE + 1.2V.
The minimum VBB output for the MAX9311 is VCC -
1.525V and the minimum VBB output for the MAX9313 is
VCC - 1.38V. Substituting the minimum VBB output for
each device into VBB = VEE + 1.2V results in a minimum
supply of 2.725V for the MAX9311 and 2.58V for the
MAX9313. Rounding up to standard supplies gives the
single-ended operating supply ranges of VCC - VEE =
3.0V to 3.8V for the MAX9311 and VCC - VEE = 2.7V to
3.8V for the MAX9313.
When using the VBB reference output, bypass it with a
0.01F ceramic capacitor to VCC. If the VBB reference is
not used, it can be left open. The VBB reference can
source or sink 0.5mA, which is sufficient to drive two
inputs. Use VBB only for inputs that are on the same
device as the VBB reference.
The maximum magnitude of the differential input from
CLK_ to CLK_ is 3.0V or VCC - VEE, whichever is less.
This limit also applies to the difference between any ref-
erence voltage input and a single-ended input.
The differential inputs have bias resistors that drive the
outputs to a differential low when the inputs are open.
The inverting inputs (CLK0 and CLK1) are biased with a
75k
pullup to VCC and a 75k pulldown to VEE. The
noninverting inputs (CLK0 and CLK1) are biased with a
75k
pulldown to VEE. The single-ended CLKSEL input
does not have a bias resistor. If not driven, pull CLKSEL
up or down with a 1kHz resistor (see Pin Description).
Specifications for the high and low voltages of a differen-
tial input (VIHD and VILD) and the differential input volt-
age (VIHD - VILD) apply simultaneously (VILD cannot be
higher than VIHD).
Output levels are referenced to VCC and are considered
LVPECL or LVECL, depending on the level of the VCC
supply. With VCC connected to a positive supply and
VEE connected to GND, the outputs are LVPECL. The
outputs are LVECL when VCC is connected to GND and
VEE is connected to a negative supply.
A single-ended input of at least VBB ±95mV or a differen-
tial input of at least 95mV switches the outputs to the
VOH and VOL levels specified in the DC Electrical
Characteristics table.
Applications Information
Supply Bypassing
Bypass VCC to VEE with high-frequency surface-mount
ceramic 0.1F and 0.01F capacitors in parallel as close
to the device as possible, with the 0.01F value capaci-
tor closest to the device. Use multiple parallel vias for
low inductance. When using the VBB reference output,
bypass it with a 0.01F ceramic capacitor to VCC (if the
VBB reference is not used, it can be left open).
Traces
Input and output trace characteristics affect the perfor-
mance of the MAX9311/MAX9313. Connect each signal
of a differential input or output to a 50
characteristic
impedance trace. Minimize the number of vias to prevent
impedance discontinuities. Reduce reflections by main-
taining the 50
characteristic impedance through con-
nectors and across cables. Reduce skew within a
相关PDF资料 |
PDF描述 |
|---|---|
| ADCLK907BCPZ-R7 | IC CLK/DATA BUFF DVR 1:1 16LFCSP |
| VE-BT4-MX | CONVERTER MOD DC/DC 48V 75W |
| VE-21Y-MU-F3 | CONVERTER MOD DC/DC 3.3V 132W |
| VI-JNY-MZ-F1 | CONVERTER MOD DC/DC 3.3V 16.5W |
| MPC905EFR2 | IC CLK BUFFER 1:6 100MHZ 16-SOIC |
相关代理商/技术参数 |
参数描述 |
|---|---|
| MAX9311ECJ+ | 功能描述:时钟驱动器及分配 LVPECL/LVECL/HSTL Clock & Data Driver RoHS:否 制造商:Micrel 乘法/除法因子:1:4 输出类型:Differential 最大输出频率:4.2 GHz 电源电压-最大: 电源电压-最小:5 V 最大工作温度:+ 85 C 封装 / 箱体:SOIC-8 封装:Reel |
| MAX9311ECJ+T | 功能描述:时钟驱动器及分配 LVPECL/LVECL/HSTL Clock & Data Driver RoHS:否 制造商:Micrel 乘法/除法因子:1:4 输出类型:Differential 最大输出频率:4.2 GHz 电源电压-最大: 电源电压-最小:5 V 最大工作温度:+ 85 C 封装 / 箱体:SOIC-8 封装:Reel |
| MAX9311ECJ-T | 功能描述:时钟缓冲器 RoHS:否 制造商:Texas Instruments 输出端数量:5 最大输入频率:40 MHz 传播延迟（最大值）: 电源电压-最大:3.45 V 电源电压-最小:2.375 V 最大功率耗散: 最大工作温度:+ 85 C 最小工作温度:- 40 C 封装 / 箱体:LLP-24 封装:Reel |
| MAX9311EGJ | 功能描述:时钟缓冲器 RoHS:否 制造商:Texas Instruments 输出端数量:5 最大输入频率:40 MHz 传播延迟（最大值）: 电源电压-最大:3.45 V 电源电压-最小:2.375 V 最大功率耗散: 最大工作温度:+ 85 C 最小工作温度:- 40 C 封装 / 箱体:LLP-24 封装:Reel |
| MAX9311EGJ-T | 功能描述:时钟缓冲器 RoHS:否 制造商:Texas Instruments 输出端数量:5 最大输入频率:40 MHz 传播延迟（最大值）: 电源电压-最大:3.45 V 电源电压-最小:2.375 V 最大功率耗散: 最大工作温度:+ 85 C 最小工作温度:- 40 C 封装 / 箱体:LLP-24 封装:Reel |
发布紧急采购，3分钟左右您将得到回复。