参数资料
型号: MAX9321EUA+
厂商: Maxim Integrated Products
文件页数: 8/9页
文件大小: 0K
描述: IC CLOCK/DATA DRIVER 1:1 8-UMAX
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 50
类型: 时钟/数据驱动器
电路数: 1
比率 - 输入:输出: 1:1
差分 - 输入:输出: 是/是
输入: HSTL,LVECL,LVPECL
输出: LVECL,LVPECL
频率 - 最大: 3GHz
电源电压: 2.25 V ~ 3.8 V
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 8-TSSOP,8-MSOP(0.118",3.00mm 宽)
供应商设备封装: 8-uMAX
包装: 管件
MAX9321/MAX9321A
Differential LVPECL/LVECL/HSTL
Receiver/Drivers
8
_______________________________________________________________________________________
When using the VBB reference output, bypass it with a
0.01F ceramic capacitor to VCC. If the VBB reference
is not used, it can be left open. The VBB reference can
source or sink 0.5mA. Use VBB only for an input on the
same device as the VBB reference.
The maximum magnitude of the differential input from D
to D is 3.0V or VCC - VEE, whichever is less. This limit
also applies to the difference between any reference
voltage input and a single-ended input.
The differential input has bias resistors that drive the
output to a differential low when the inputs are open.
The inverting input is biased with a 60k
pullup to VCC
and a 100k
pulldown to VEE. The noninverting input is
biased with a 100k
pulldown to VEE.
Specifications for the high and low voltage of the differ-
ential input (VIHD and VILD) and the differential input
voltage (VIHD - VILD) apply simultaneously (VILD cannot
be higher than VIHD).
Outputs
Output levels are referenced to VCC and are consid-
ered LVPECL or LVECL, depending on the level of the
VCC supply. With VCC connected to a positive supply
and VEE connected to GND, the output is LVPECL. The
output is LVECL when VCC is connected to GND and
VEE is connected to a negative supply.
A single-ended input of at least VBB ±100mV or a differ-
ential input of at least ±100mV switches the outputs to
the VOH and VOL levels specified in the DC Electrical
Characteristics table.
Applications Information
Supply Bypassing
Bypass VCC to VEE with high-frequency surface-mount
ceramic 0.1F and 0.01F capacitors in parallel as
close to the device as possible, with the 0.01F value
capacitor closest to the device. Use multiple parallel
vias for low inductance. When using the VBB reference
output, bypass it with a 0.01F ceramic capacitor to
VCC (if the VBB reference is not used, it can be left
open).
Traces
Input and output trace characteristics affect the perfor-
mance of the MAX9321/MAX9321A. Connect each sig-
nal of a differential input or output to a 50
characteristic impedance trace. Minimize the number of
vias to prevent impedance discontinuities. Reduce
reflections by maintaining the 50
characteristic
impedance through connectors and across cables.
Reduce skew within a differential pair by matching the
electrical length of the traces.
The exposed-pad (EP) SO package can be soldered to
the PC board for enhanced thermal performance. If the
EP is not soldered to the PC board, the thermal resis-
tance is the same as the regular SO package. The EP is
connected to the chip VEE supply. Be sure that the pad
does not touch signal lines or other supplies.
Contact Maxim's Packaging department for guidelines
on the use of EP packages.
Output Termination
Terminate outputs through 50
to VCC - 2V or use an
equivalent Thevenin termination. When a single-ended
signal is taken from the differential output, terminate
both outputs. For example, when Q is used as a single-
ended output, terminate both Q and Q.
Chip Information
TRANSISTOR COUNT: 162
6
SOT23
D
VCC 1
2
3
4
8
5
7
VEE
MAX9321A
60k
100k
100k
VCC
VEE
6
MAX/SO
1
2
3
4
8
5
7
MAX9321A
D
N.C.
VBB
Q
60k
100k
100k
VCC
Q
VEE
VCC
N.C.
VBB
D
Q
D
Pin Configurations (continued)
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