参数资料
型号: MAX9402EHJ+T
厂商: Maxim Integrated Products
文件页数: 7/13页
文件大小: 0K
描述: IC BUFF/RCVR DIFF QUAD 32TQFP
标准包装: 2,500
类型: 收发器
驱动器/接收器数: 4/4
电源电压: 2.375 V ~ 5.5 V
安装类型: 表面贴装
封装/外壳: 32-TQFP
供应商设备封装: 32-TQFP(5x5)
包装: 带卷 (TR)
MAX9400/MAX9402/MAX9403/MAX9405
Quad Differential LVECL/LVPECL
Buffer/Receivers
_______________________________________________________________________________________
3
AC ELECTRICAL CHARACTERISTICS
(VCC - VEE = 2.375V to 5.5V, outputs terminated with 50
±1% to VCC - 2.0V, enabled, CLK = 3.2GHz, fIN = 1.6GHz, input transition
time = 125ps (20% to 80%), VIHD = VEE + 1.2V to VCC, VILD = VEE to VCC - 0.2V, VIHD - VILD = 0.2V to smaller of |VCC - VEE| or 3V,
unless otherwise noted. Typical values are at VCC - VEE = 3.3V, VIHD = VCC - 0.9V, VILD = VCC 1.7V, TA = +25°C, unless otherwise
noted.) (Notes 1, 4)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
MAX9400/MAX9403
237
335
437
IN-to-OUT Differential
Propagation Delay
tPLH1
tPHL1
MAX9402/MAX9405
SEL = high, Figure 3
237
335
437
ps
MAX9400/MAX9403
397
475
597
CLK-to-OUT Differential
Propagation Delay
tPLH2
tPHL2
MAX9402/MAX9405
SEL = low, Figure 4
397
475
597
ps
IN-to-OUT Channel-to-Channel
Skew (Note 5)
tSKD1
SEL = high
16
80
ps
CLK-to-OUT Channel-to-
Channel Skew (Note 5)
tSKD2
SEL = low
8
55
ps
Maximum Clock Frequency
fCLK(MAX)
VOH - VOL
≥ 500mV, SEL = low
3.0
GHz
Maximum Data Frequency
fIN(MAX)
VOH - VOL
≥ 400mV, SEL = high
2
GHZ
SEL = low, fCLK = 3.0GHz clock, fIN = 1.5GHz
0.64
1.3
Added Random Jitter (Note 6)
tRJ
SEL = high, fIN = 2GHz
0.74
1.5
ps(RMS)
SEL = low, fCLK = 3.0GHz, IN_ = 3.0Gbps
2
23 - 1 PRBS pattern
17
30
Added Deterministic Jitter
(Note 6)
tDJ
SEL = high, IN = 2.0Gbps 2
23 - 1 PRBS
pattern
40
55
ps(P-P)
IN-to-CLK Setup Time
tS
Figure 4
80
ps
CLK-to-IN Hold Time
tH
Figure 4
80
ps
Output Rise Time
tR
Figure 3
80
120
ps
Output Fall Time
tF
Figure 3
80
120
ps
Propagation Delay Temperature
Coefficient
tPD/
T
0.2
1
ps/°C
Note 1: Measurements are made with the device in thermal equilibrium.
Note 2: Current into a pin is defined as positive. Current out of a pin is defined as negative.
Note 3: DC parameters are production tested at +25°C. DC limits are guaranteed by design and characterization over the full oper-
ating temperature range.
Note 4: Guaranteed by design and characterization. Limits are set to ±6 sigma.
Note 5: Measured between outputs of the same part at the signal crossing points for a same-edge transition.
Note 6: Device jitter added to the input signal.
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