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参数资料
| 型号： | MAX9491ETP080+T |
| 厂商： | Maxim Integrated Products |
| 文件页数： | 8/11页 |
| 文件大小： | 0K |
| 描述： | IC FACT-PROG PLL CLK GEN 20-TQFN |
| 产品培训模块： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 标准包装： | 2,500 |
| 类型： | PLL 时钟发生器 |
| PLL： | 是 |
| 输入： | LVCMOS，晶体 |
| 输出： | LVCMOS |
| 电路数： | 1 |
| 比率 - 输入:输出： | 1:1 |
| 差分 - 输入:输出： | 无/无 |
| 频率 - 最大： | 200MHz |
| 除法器/乘法器： | 无/无 |
| 电源电压： | 3 V ~ 3.6 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 20-WQFN 裸露焊盘 |
| 供应商设备封装： | 20-TQFN-EP（5x5） |
| 包装： | 带卷 (TR) |
MAX9491
Factory Programmable Single PLL
Clock Generator
6
_______________________________________________________________________________________
Detailed Description
The MAX9491 features a programmable fractional-N
PLL, so frequencies between 4MHz to 200MHz can be
generated. The device provides a buffered PLL clock
output. The crystal input frequency can be between
5MHz and 35MHz, and the clock input between 5MHz
and 50MHz. The internal VCXO has a fine-tuning range
of ±200ppm.
Power-Down
Driving
PD low places the MAX9491 in power-down
mode.
PD then sets CLK_OUT to high impedance and
shuts down the PLL. CLK_OUT has an 80k
(typ) inter-
nal pulldown resistor.
Voltage-Controlled Crystal Oscillator
(VCXO)
The MAX9491’s internal VCXO produces a reference
clock for the PLL used to generate the CLK_OUT. The
oscillator uses a crystal as the base frequency refer-
ence and has a voltage-controlled tuning input for micro
adjustment in a ±200ppm range. The tuning voltage,
VTUNE, can vary from 0 to 3V as shown in Figure 1. The
crystal should be AT-cut and oscillate on its fundamen-
tal mode with ±30ppm. The crystal shunt capacitor
Pin Description
Typical Operating Circuit/Block Diagram
+3.3V
VDD
VDDA
VDD
0.1
F x 3
0.1
F
MAX9491
+3.3V
GND
AGND
TUNE
C1
C2
CLK_OUT
PLL
VCXO
X1
OR REFERENCE
INPUT
X2
OTP
PD
PIN
TQFN
TSSOP
NAME
FUNCTION
1
5
TUNE
VCXO Tune Voltage Input. If using a reference clock input or VCXO is not used,
connect TUNE to VDD.
2—
VDDA
Analog Power Supply. Bypass to GND with a 0.1F capacitor.
3
—
AGND
Analog Ground
4, 10, 11
6, 9, 11
GND
Ground
5
7
CLK_OUT
Output Clock. Internally pulled down.
6–9, 14, 19, 20
2, 3, 8, 10
I.C.
Internally Connected. Leave unconnected for normal operation.
12, 13, 16
4, 12
VDD
Power Supply. Bypass to GND with a 0.1F capacitor.
15
13
PD
Active-Low Power-Down Input. Pull high for normal operation. Drive
PD low to place
MAX9491 in power-down mode. Internally pulled down.
17
14
X2
Crystal Connection 2. Leave unconnected if using a reference clock.
18
1
X1
Crystal Connection 1 or Reference Clock Input
EP
—
EP
Exposed Paddle (TQFN Only). Connect EP to GND or leave unconnected.
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相关代理商/技术参数 |
参数描述 |
|---|---|
| MAX9491ETP095 | 功能描述:时钟发生器及支持产品 RoHS:否 制造商:Silicon Labs 类型:Clock Generators 最大输入频率:14.318 MHz 最大输出频率:166 MHz 输出端数量:16 占空比 - 最大:55 % 工作电源电压:3.3 V 工作电源电流:1 mA 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:QFN-56 |
| MAX9491ETP095+ | 功能描述:时钟发生器及支持产品 Factory-Prog Single PLL Clock Generator RoHS:否 制造商:Silicon Labs 类型:Clock Generators 最大输入频率:14.318 MHz 最大输出频率:166 MHz 输出端数量:16 占空比 - 最大:55 % 工作电源电压:3.3 V 工作电源电流:1 mA 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:QFN-56 |
| MAX9491ETP095+T | 功能描述:时钟发生器及支持产品 Factory-Prog Single PLL Clock Generator RoHS:否 制造商:Silicon Labs 类型:Clock Generators 最大输入频率:14.318 MHz 最大输出频率:166 MHz 输出端数量:16 占空比 - 最大:55 % 工作电源电压:3.3 V 工作电源电流:1 mA 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:QFN-56 |
| MAX9491ETP095-T | 功能描述:时钟发生器及支持产品 RoHS:否 制造商:Silicon Labs 类型:Clock Generators 最大输入频率:14.318 MHz 最大输出频率:166 MHz 输出端数量:16 占空比 - 最大:55 % 工作电源电压:3.3 V 工作电源电流:1 mA 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:QFN-56 |
| MAX9491EUD | 制造商:Maxim Integrated Products 功能描述:FACTORY-PROGRAMMABLE SINGLE PLL CLO - Rail/Tube |
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