参数资料
型号: MAX9526ATJ+T
厂商: Maxim Integrated Products
文件页数: 13/38页
文件大小: 0K
描述: IC VID DECODER NTSC/PAL 32-TQFN
其它有关文件: Automotive Product Guide
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 2,500
类型: 视频解码器
应用: 车载系统,播放器,电视
电压 - 电源,模拟: 1.8V
电压 - 电源,数字: 1.8V
安装类型: 表面贴装
封装/外壳: 32-WFQFN 裸露焊盘
供应商设备封装: 32-TQFN-EP(5x6)
包装: 带卷 (TR)
Low-Power, High-Performance
NTSC/PAL Video Decoder
Read Data Format
Send the slave address with the R/W bit set to 1 to initi-
ate a read operation. The MAX9526 acknowledges
receipt of its slave address by pulling SDA low during
the 9th SCL clock pulse. A START command followed
by a read command resets the address pointer to reg-
ister 0x00.
The first byte transmitted from the MAX9526 is the con-
tents of register 0x00. Transmitted data is valid on the
rising edge of SCL. The address pointer autoincre-
ments after each read data byte. This autoincrement
feature allows all registers to be read sequentially within
one continuous frame. A STOP condition can be issued
after any number of read data bytes. If a STOP condi-
tion is issued followed by another read operation, the
first data byte to be read is from register 0x00.
The address pointer can be preset to a specific register
before a read command is issued. The master presets
the address pointer by first sending the MAX9526’s
slave address with the R/W bit set to 0 followed by the
register address. A REPEATED START condition is then
sent followed by the slave address with the R/W bit set
to 1. The MAX9526 then transmits the contents of the
specified register. The address pointer autoincrements
after transmitting the first byte.
The master acknowledges receipt of each read byte
during the acknowledge clock pulse. The master must
acknowledge all correctly received bytes except the
last byte. The final byte must be followed by a not
acknowledge from the master and then a STOP condi-
tion. Figure 15 illustrates the frame format for reading
one byte from the MAX9526. Figure 16 illustrates the
frame format for reading multiple bytes from the
MAX9526.
SCL
SDA
START
CONDITION
STOP
CONDITION
REPEATED
START CONDITION
START
CONDITION
tHD, STA
tSU, STA
tHD, STA
tSP
tBUF
tSU, STO
tLOW
tSU, DAT
tHD, DAT
tHIGH
tR
tF
Figure 10. I2C Serial Interface Timing Diagram
1
SCL
START
CONDITION
SDA
28
9
CLOCK PULSE FOR
ACKNOWLEDGMENT
ACKNOWLEDGE
NOT ACKNOWLEDGE
Figure 12. Acknowledge
SCL
SDA
SSr
P
Figure 11. START, STOP, and REPEATED START Conditions
MAX9526
20
Maxim Integrated
相关PDF资料
PDF描述
MAX9526AEI/V+ IC VID DECODER NTSC/PAL 28QSOP
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VE-2NJ-IY-F3 CONVERTER MOD DC/DC 36V 50W
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