参数资料
型号: MAX9601EUP+T
厂商: Maxim Integrated Products
文件页数: 3/12页
文件大小: 0K
描述: IC COMPARATOR HS 20-TSSOP
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 2,500
类型: 带锁销
元件数: 2
输出类型: 补充型,差分,PECL
电压 - 输入偏移(最小值): 5mV @ -5.2V,5V
电流 - 输入偏压(最小值): 6µA @ -5.2V,5V
电流 - 输出(标准): 50mA
电流 - 静态(最大值): 27mA
CMRR, PSRR(标准): 70dB CMRR,65dB PSRR
传输延迟(最大): 0.5ns
磁滞: 30mV
工作温度: -40°C ~ 85°C
封装/外壳: 20-TSSOP(0.173",4.40mm 宽)
安装类型: 表面贴装
包装: 带卷 (TR)
MAX9600/MAX9601/MAX9602
Dual ECL and Dual/Quad PECL, 500ps,
Ultra-High-Speed Comparators
______________________________________________________________________________________
11
Timing Information (MAX9600/MAX9601)
The timing diagram (Figure 1) illustrates the operation
of a comparator with latch enable. The top line of the
diagram illustrates a latch-enable pulse. Initially, the
latch-enable input (LE, LE_) is differentially high, which
places the comparator in latch mode. When the input
signal (IN_+, IN_-) switches from low to high, the output
(Q_, Q_) remains latched to the previous low state.
When the latch-enable input goes differentially low,
starting the compare function, the output responds to
the input and transitions to high after a time (tLPD). The
leading edges of the subsequent input signal switch
the comparator after time interval tPD+ or tPD- (depend-
ing on the direction of the input transitions) until a high
latch-enable pulse places the device in latch mode
again. The input signal must occur at minimum time
(tLS) before the latch rising edge, and must maintain its
state for at least tLH after the rising edge. A minimum
latch-pulse width (tLPW) of 250ps (typ) is needed for
proper latch operation.
ECL/PCL
The MAX9600/MAX9601/MAX9602 outputs are emitter
followers that require external resistive connections to a
voltage source (VT) more negative than the lowest VOL
for proper static and dynamic operation. When properly
terminated, the outputs provide appropriate levels, VOL
or VOH, for ECL (MAX9600) or PECL (MAX9601/
MAX9602). Output-current polarity always sinks into the
termination scheme during proper operation.
ECL-output signal levels are referenced to GND, and
PECL-output signals are referenced to VCCO_.
Chip Information
MAX9600 TRANSISTOR COUNT: 558
MAX9601 TRANSISTOR COUNT: 600
MAX9602 TRANSISTOR COUNT: 608
PROCESS: Bipolar
20
19
18
17
16
15
14
13
1
2
3
4
5
6
7
8
QB
VCCOB
LEB
LEA
VCCOA
QA
LEB
VEE
VCC
HYSB
HYSA
VCC
VEE
LEA
12
11
9
10
INB-
INB+
INA+
INA-
MAX9601
TSSOP-20
24
23
22
21
20
19
18
17
1
2
3
4
5
6
7
8
VCCOA
QA
VCCOB
INB+
VEE
INA-
INA+
QB
VCCOC
QC
INC-
INC+
VCC
INB-
16
15
14
13
9
10
11
12
QC
VCCOD
QD
VCC
IND-
IND+
VEE
TSSOP-24
MAX9602
20
19
18
17
16
15
14
13
1
2
3
4
5
6
7
8
QB
GND
LEB
LEA
GND
QA
TOP VIEW
LEB
VEE
VCC
HYSB
HYSA
VCC
VEE
LEA
12
11
9
10
INB-
INB+
INA+
INA-
MAX9600
TSSOP-20
Pin Configurations
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